diff --git a/projects/adrv9009/a10gx/Makefile b/projects/adrv9009/a10gx/Makefile deleted file mode 100644 index 52a8169e8..000000000 --- a/projects/adrv9009/a10gx/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := adrv9009_a10gx - -M_DEPS += ../common/adrv9009_qsys.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/intel/dacfifo_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += intel/adi_jesd204 -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 - -include ../../scripts/project-intel.mk diff --git a/projects/adrv9009/a10gx/system_constr.sdc b/projects/adrv9009/a10gx/system_constr.sdc deleted file mode 100644 index 4d4b26248..000000000 --- a/projects/adrv9009/a10gx/system_constr.sdc +++ /dev/null @@ -1,12 +0,0 @@ - -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "4.06504065 ns" -name ref_clk0 [get_ports {ref_clk0}] -create_clock -period "4.06504065 ns" -name ref_clk1 [get_ports {ref_clk1}] - -derive_pll_clocks -derive_clock_uncertainty - -set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] - -set_false_path -from * -to [get_ports {flash_resetn}] - diff --git a/projects/adrv9009/a10gx/system_project.tcl b/projects/adrv9009/a10gx/system_project.tcl deleted file mode 100644 index 7de10f0f8..000000000 --- a/projects/adrv9009/a10gx/system_project.tcl +++ /dev/null @@ -1,143 +0,0 @@ -source ../../../scripts/adi_env.tcl -source ../../scripts/adi_project_intel.tcl - -adi_project adrv9009_a10gx - -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl - -# lane interface - -set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "ref_clk0(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_AJ8 -to ref_clk1 ; ## B20 FMCA_GBTCLK1_M2C_P -set_location_assignment PIN_AJ7 -to "ref_clk1(n)" ; ## B21 FMCA_GBTCLK1_M2C_N -set_location_assignment PIN_BA7 -to rx_serial_data[0] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_serial_data[0](n)" ; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AY5 -to rx_serial_data[1] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_serial_data[1](n)" ; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_AW7 -to rx_serial_data[2] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_serial_data[2](n)" ; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_AV5 -to rx_serial_data[3] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_serial_data[3](n)" ; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_BD5 -to tx_serial_data[0] ; ## A22 FMCA_DP1_C2M_P (tx_serial_data_p[0]) -set_location_assignment PIN_BD6 -to "tx_serial_data[0](n)" ; ## A23 FMCA_DP1_C2M_N (tx_serial_data_n[0]) -set_location_assignment PIN_BB5 -to tx_serial_data[1] ; ## A26 FMCA_DP2_C2M_P (tx_serial_data_p[1]) -set_location_assignment PIN_BB6 -to "tx_serial_data[1](n)" ; ## A27 FMCA_DP2_C2M_N (tx_serial_data_n[1]) -set_location_assignment PIN_BC7 -to tx_serial_data[2] ; ## C02 FMCA_DP0_C2M_P (tx_serial_data_p[2]) -set_location_assignment PIN_BC8 -to "tx_serial_data[2](n)" ; ## C03 FMCA_DP0_C2M_N (tx_serial_data_n[2]) -set_location_assignment PIN_BC3 -to tx_serial_data[3] ; ## A30 FMCA_DP3_C2M_P (tx_serial_data_p[3]) -set_location_assignment PIN_BC4 -to "tx_serial_data[3](n)" ; ## A31 FMCA_DP3_C2M_N (tx_serial_data_n[3]) - -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data - -set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 -set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data - -# Merge RX and TX into single transceiver -for {set i 0} {$i < 4} {incr i} { - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] -} - -set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P -set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N -set_location_assignment PIN_AY15 -to rx_os_sync ; ## G27 FMCA_HPC_LA25_P (Sniffer) -set_location_assignment PIN_AY14 -to rx_os_sync(n) ; ## G28 FMCA_HPC_LA25_N (Sniffer) -set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_HPC_LA02_P -set_location_assignment PIN_AT22 -to tx_sync(n) ; ## H08 FMCA_HPC_LA02_N -set_location_assignment PIN_AV15 -to sysref ; ## G06 FMC_HPC_LA00_CC_P -set_location_assignment PIN_AU15 -to sysref(n) ; ## G07 FMC_HPC_LA00_CC_N -set_location_assignment PIN_BB15 -to tx_sync_1 ; ## H28 FMC_HPC_LA24_P -set_location_assignment PIN_BC15 -to tx_sync_1(n) ; ## H29 FMC_HPC_LA24_N - - -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync -set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync -set_instance_assignment -name IO_STANDARD LVDS -to tx_sync -set_instance_assignment -name IO_STANDARD LVDS -to sysref -set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_1 -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_1 -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref - -set_location_assignment PIN_AV13 -to spi_csn_ad9528 ; ## D15 FMCA_HPC_LA09_N -set_location_assignment PIN_AW13 -to spi_csn_adrv9009 ; ## D14 FMCA_HPC_LA09_P -set_location_assignment PIN_AT17 -to spi_clk ; ## H13 FMCA_HPC_LA07_P -set_location_assignment PIN_AU17 -to spi_mosi ; ## H14 FMCA_HPC_LA07_N -set_location_assignment PIN_AP18 -to spi_miso ; ## G12 FMCA_HPC_LA08_P - -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9009 -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso - -set_location_assignment PIN_AT19 -to ad9528_reset_b ; ## D26 FMCA_HPC_LA26_P -set_location_assignment PIN_AT20 -to ad9528_sysref_req ; ## D27 FMCA_HPC_LA26_N -set_location_assignment PIN_AR17 -to adrv9009_tx1_enable ; ## D17 FMCA_HPC_LA13_P -set_location_assignment PIN_AW18 -to adrv9009_tx2_enable ; ## C18 FMCA_HPC_LA14_P -set_location_assignment PIN_AP17 -to adrv9009_rx1_enable ; ## D18 FMCA_HPC_LA13_N -set_location_assignment PIN_AV18 -to adrv9009_rx2_enable ; ## C19 FMCA_HPC_LA14_N -set_location_assignment PIN_AT14 -to adrv9009_test ; ## H16 FMC_HPC_LA11_P -set_location_assignment PIN_AN20 -to adrv9009_reset_b ; ## H10 FMCA_HPC_LA04_P -set_location_assignment PIN_AP19 -to adrv9009_gpint ; ## H11 FMCA_HPC_LA04_N - -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx1_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_tx2_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx1_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_rx2_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_test -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_reset_b -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpint - -# single ended default - -set_location_assignment PIN_AR9 -to adrv9009_gpio[0] ; ## H19 FMCA_HPC_LA15_P -set_location_assignment PIN_AT9 -to adrv9009_gpio[1] ; ## H20 FMCA_HPC_LA15_N -set_location_assignment PIN_AT13 -to adrv9009_gpio[2] ; ## G18 FMCA_HPC_LA16_P -set_location_assignment PIN_AU13 -to adrv9009_gpio[3] ; ## G19 FMCA_HPC_LA16_N -set_location_assignment PIN_AY10 -to adrv9009_gpio[4] ; ## H25 FMCA_HPC_LA21_P -set_location_assignment PIN_AY11 -to adrv9009_gpio[5] ; ## H26 FMCA_HPC_LA21_N -set_location_assignment PIN_AU21 -to adrv9009_gpio[6] ; ## C22 FMCA_HPC_LA18_CC_P -set_location_assignment PIN_AV21 -to adrv9009_gpio[7] ; ## C23 FMCA_HPC_LA18_CC_N -set_location_assignment PIN_AY12 -to adrv9009_gpio[8] ; ## G25 FMCA_HPC_LA22_N (LVDS_1N) -set_location_assignment PIN_AU11 -to adrv9009_gpio[9] ; ## H22 FMCA_HPC_LA19_P (LVDS_2P) -set_location_assignment PIN_AU12 -to adrv9009_gpio[10] ; ## H23 FMCA_HPC_LA19_N (LVDS_2N) -set_location_assignment PIN_AU8 -to adrv9009_gpio[11] ; ## G21 FMCA_HPC_LA20_P (LVDS_3P) -set_location_assignment PIN_AT8 -to adrv9009_gpio[12] ; ## G22 FMCA_HPC_LA20_N (LVDS_3N) -set_location_assignment PIN_AP16 -to adrv9009_gpio[13] ; ## G16 FMC_HPC_LA12_N (LVDS_4N) -set_location_assignment PIN_AR16 -to adrv9009_gpio[14] ; ## G15 FMC_HPC_LA12_P (LVDS_4P) -set_location_assignment PIN_AW12 -to adrv9009_gpio[15] ; ## G24 FMCA_HPC_LA22_P (LVDS_1P) -set_location_assignment PIN_AW14 -to adrv9009_gpio[16] ; ## C11 FMC_HPC_LA06_N (LVDS_5N) -set_location_assignment PIN_AV14 -to adrv9009_gpio[17] ; ## C10 FMC_HPC_LA06_P (LVDS_5P) -set_location_assignment PIN_AW11 -to adrv9009_gpio[18] ; ## D12 FMCA_HPC_LA05_N - -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9009_gpio[18] - -# set optimization to get a better timing closure -#set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" - -execute_flow -compile diff --git a/projects/adrv9009/a10gx/system_qsys.tcl b/projects/adrv9009/a10gx/system_qsys.tcl deleted file mode 100644 index 94b105eac..000000000 --- a/projects/adrv9009/a10gx/system_qsys.tcl +++ /dev/null @@ -1,20 +0,0 @@ -set dac_fifo_address_width 10 - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl -source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl - -if [info exists ad_project_dir] { - source ../../common/adrv9009_qsys.tcl -} else { - source ../common/adrv9009_qsys.tcl -} - -#system ID -set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} -set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} - -set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" - -sysid_gen_sys_init_file; - diff --git a/projects/adrv9009/a10gx/system_top.v b/projects/adrv9009/a10gx/system_top.v deleted file mode 100644 index d05aae6b6..000000000 --- a/projects/adrv9009/a10gx/system_top.v +++ /dev/null @@ -1,243 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - input sys_resetn, - - // ddr3 - - output ddr3_clk_p, - output ddr3_clk_n, - output [ 14:0] ddr3_a, - output [ 2:0] ddr3_ba, - output ddr3_cke, - output ddr3_cs_n, - output ddr3_odt, - output ddr3_reset_n, - output ddr3_we_n, - output ddr3_ras_n, - output ddr3_cas_n, - inout [ 7:0] ddr3_dqs_p, - inout [ 7:0] ddr3_dqs_n, - inout [ 63:0] ddr3_dq, - output [ 7:0] ddr3_dm, - input ddr3_rzq, - input ddr3_ref_clk, - - // ethernet - - input eth_ref_clk, - input eth_rxd, - output eth_txd, - output eth_mdc, - inout eth_mdio, - output eth_resetn, - input eth_intn, - - // board gpio - - input [ 10:0] gpio_bd_i, - output [ 15:0] gpio_bd_o, - - // flash - - output flash_oen, - output [ 1:0] flash_cen, - output [ 27:0] flash_addr, - inout [ 31:0] flash_data, - output flash_wen, - output flash_advn, - output flash_clk, - output flash_resetn, - - // lane interface - - input ref_clk0, - input ref_clk1, - input [ 3:0] rx_serial_data, - output [ 3:0] tx_serial_data, - output rx_sync, - output rx_os_sync, - input tx_sync, - input tx_sync_1, - input sysref, - - output ad9528_reset_b, - output ad9528_sysref_req, - output adrv9009_tx1_enable, - output adrv9009_tx2_enable, - output adrv9009_rx1_enable, - output adrv9009_rx2_enable, - output adrv9009_test, - output adrv9009_reset_b, - input adrv9009_gpint, - - inout [ 18:0] adrv9009_gpio, - - output spi_csn_ad9528, - output spi_csn_adrv9009, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire eth_reset; - wire eth_mdio_i; - wire eth_mdio_o; - wire eth_mdio_t; - wire [ 63:0] gpio_i; - wire [ 63:0] gpio_o; - wire [ 7:0] spi_csn_s; - wire dac_fifo_bypass; - wire [23:0] flash_addr_raw; - - // assignments - - assign spi_csn_ad9528 = spi_csn_s[0]; - assign spi_csn_adrv9009 = spi_csn_s[1]; - - // gpio (adrv9009) - - assign gpio_i[63:61] = gpio_o[63:61]; - - assign dac_fifo_bypass = gpio_o[60]; - assign gpio_i[60:60] = gpio_o[60:60]; - - assign ad9528_reset_b = gpio_o[59]; - assign ad9528_sysref_req = gpio_o[58]; - assign adrv9009_tx1_enable = gpio_o[57]; - assign adrv9009_tx2_enable = gpio_o[56]; - assign adrv9009_rx1_enable = gpio_o[55]; - assign adrv9009_rx2_enable = gpio_o[54]; - assign adrv9009_test = gpio_o[53]; - assign adrv9009_reset_b = gpio_o[52]; - assign gpio_i[59:52] = gpio_o[59:52]; - - assign gpio_i[51:51] = adrv9009_gpint; - - assign gpio_i[50:32] = gpio_o[50:32]; - - // board stuff - - assign eth_resetn = ~eth_reset; - assign eth_mdio_i = eth_mdio; - assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; - - assign ddr3_a[14:12] = 3'd0; - - assign gpio_i[31:27] = gpio_o[31:27]; - assign gpio_i[26:16] = gpio_bd_i; - assign gpio_i[15: 0] = gpio_o[15: 0]; - - assign gpio_bd_o = gpio_o[15:0]; - - // User code space at offset 0x0930_0000 per Altera's Board Update Portal - // reference design used to program flash - - assign flash_addr = flash_addr_raw + 28'h9300000; - - // Common Flash interface assignments - - assign flash_resetn = 1'b1; - assign flash_advn = 1'b0; - assign flash_clk = 1'b0; - assign flash_cen[1] = flash_cen[0]; - - system_bd i_system_bd ( - .adrv9009_gpio_export (adrv9009_gpio), - .sys_clk_clk (sys_clk), - .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .sys_ethernet_mdio_mdc (eth_mdc), - .sys_ethernet_mdio_mdio_in (eth_mdio_i), - .sys_ethernet_mdio_mdio_out (eth_mdio_o), - .sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .sys_ethernet_ref_clk_clk (eth_ref_clk), - .sys_ethernet_reset_reset (eth_reset), - .sys_ethernet_sgmii_rxp_0 (eth_rxd), - .sys_ethernet_sgmii_txp_0 (eth_txd), - .sys_gpio_bd_in_port (gpio_i[31:0]), - .sys_gpio_bd_out_port (gpio_o[31:0]), - .sys_gpio_in_export (gpio_i[63:32]), - .sys_gpio_out_export (gpio_o[63:32]), - .pr_rom_data_nc_rom_data('h0), - .sys_rst_reset_n (sys_resetn), - .sys_spi_MISO (spi_miso), - .sys_spi_MOSI (spi_mosi), - .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n (spi_csn_s), - .tx_serial_data_tx_serial_data (tx_serial_data), - .tx_fifo_bypass_bypass (dac_fifo_bypass), - .tx_ref_clk_clk (ref_clk1), - .tx_sync_export (tx_sync), - .tx_sysref_export (sysref), - .rx_serial_data_rx_serial_data (rx_serial_data[1:0]), - .rx_os_serial_data_rx_serial_data (rx_serial_data[3:2]), - .rx_os_ref_clk_clk (ref_clk1), - .rx_os_sync_export (rx_os_sync), - .rx_os_sysref_export (sysref), - .rx_ref_clk_clk (ref_clk1), - .rx_sync_export (rx_sync), - .rx_sysref_export (sysref), - .sys_flash_tcm_address_out (flash_addr_raw), - .sys_flash_tcm_read_n_out (flash_oen), - .sys_flash_tcm_write_n_out (flash_wen), - .sys_flash_tcm_data_out (flash_data), - .sys_flash_tcm_chipselect_n_out (flash_cen[0])); - -endmodule diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile deleted file mode 100644 index 060e2cffa..000000000 --- a/projects/adrv9371x/a10gx/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := adrv9371x_a10gx - -M_DEPS += ../common/adrv9371x_qsys.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/intel/dacfifo_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += intel/adi_jesd204 -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 - -include ../../scripts/project-intel.mk diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc deleted file mode 100644 index 6c78e9e61..000000000 --- a/projects/adrv9371x/a10gx/system_constr.sdc +++ /dev/null @@ -1,12 +0,0 @@ - -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "8.1300813 ns" -name ref_clk0 [get_ports {ref_clk0}] -create_clock -period "8.1300813 ns" -name ref_clk1 [get_ports {ref_clk1}] - -derive_pll_clocks -derive_clock_uncertainty - -set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] - -set_false_path -from * -to [get_ports {flash_resetn}] - diff --git a/projects/adrv9371x/a10gx/system_project.tcl b/projects/adrv9371x/a10gx/system_project.tcl deleted file mode 100644 index 94f904045..000000000 --- a/projects/adrv9371x/a10gx/system_project.tcl +++ /dev/null @@ -1,139 +0,0 @@ -source ../../../scripts/adi_env.tcl -source ../../scripts/adi_project_intel.tcl - -adi_project adrv9371x_a10gx - -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl - -# lane interface - -set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "ref_clk0(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_AJ8 -to ref_clk1 ; ## B20 FMCA_GBTCLK1_M2C_P -set_location_assignment PIN_AJ7 -to "ref_clk1(n)" ; ## B21 FMCA_GBTCLK1_M2C_N -set_location_assignment PIN_BA7 -to rx_serial_data[0] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_serial_data[0](n)" ; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AY5 -to rx_serial_data[1] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_serial_data[1](n)" ; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_AW7 -to rx_serial_data[2] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_serial_data[2](n)" ; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_AV5 -to rx_serial_data[3] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_serial_data[3](n)" ; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_BD5 -to tx_serial_data[0] ; ## A22 FMCA_DP1_C2M_P (tx_serial_data_p[0]) -set_location_assignment PIN_BD6 -to "tx_serial_data[0](n)" ; ## A23 FMCA_DP1_C2M_N (tx_serial_data_n[0]) -set_location_assignment PIN_BB5 -to tx_serial_data[1] ; ## A26 FMCA_DP2_C2M_P (tx_serial_data_p[1]) -set_location_assignment PIN_BB6 -to "tx_serial_data[1](n)" ; ## A27 FMCA_DP2_C2M_N (tx_serial_data_n[1]) -set_location_assignment PIN_BC7 -to tx_serial_data[2] ; ## C02 FMCA_DP0_C2M_P (tx_serial_data_p[2]) -set_location_assignment PIN_BC8 -to "tx_serial_data[2](n)" ; ## C03 FMCA_DP0_C2M_N (tx_serial_data_n[2]) -set_location_assignment PIN_BC3 -to tx_serial_data[3] ; ## A30 FMCA_DP3_C2M_P (tx_serial_data_p[3]) -set_location_assignment PIN_BC4 -to "tx_serial_data[3](n)" ; ## A31 FMCA_DP3_C2M_N (tx_serial_data_n[3]) - -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data - -set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 -set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data - -# Merge RX and TX into single transceiver -for {set i 0} {$i < 4} {incr i} { - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] -} - -set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P -set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N -set_location_assignment PIN_AY15 -to rx_os_sync ; ## G27 FMCA_HPC_LA25_P (Sniffer) -set_location_assignment PIN_AY14 -to rx_os_sync(n) ; ## G28 FMCA_HPC_LA25_N (Sniffer) -set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_HPC_LA02_P -set_location_assignment PIN_AT22 -to tx_sync(n) ; ## H08 FMCA_HPC_LA02_N -set_location_assignment PIN_AY17 -to sysref ; ## G36 FMCA_HPC_LA33_P -set_location_assignment PIN_AW17 -to sysref(n) ; ## G37 FMCA_HPC_LA33_N - -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync -set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync -set_instance_assignment -name IO_STANDARD LVDS -to tx_sync -set_instance_assignment -name IO_STANDARD LVDS -to sysref -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref - -set_location_assignment PIN_AW13 -to spi_csn_ad9371 ; ## D14 FMCA_HPC_LA09_P -set_location_assignment PIN_AV13 -to spi_csn_ad9528 ; ## D15 FMCA_HPC_LA09_N -set_location_assignment PIN_AT17 -to spi_clk ; ## H13 FMCA_HPC_LA07_P -set_location_assignment PIN_AU17 -to spi_mosi ; ## H14 FMCA_HPC_LA07_N -set_location_assignment PIN_AP18 -to spi_miso ; ## G12 FMCA_HPC_LA08_P - -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371 -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi -set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso - -set_location_assignment PIN_AT19 -to ad9528_reset_b ; ## D26 FMCA_HPC_LA26_P -set_location_assignment PIN_AT20 -to ad9528_sysref_req ; ## D27 FMCA_HPC_LA26_N -set_location_assignment PIN_AR17 -to ad9371_tx1_enable ; ## D17 FMCA_HPC_LA13_P -set_location_assignment PIN_AW18 -to ad9371_tx2_enable ; ## C18 FMCA_HPC_LA14_P -set_location_assignment PIN_AP17 -to ad9371_rx1_enable ; ## D18 FMCA_HPC_LA13_N -set_location_assignment PIN_AV18 -to ad9371_rx2_enable ; ## C19 FMCA_HPC_LA14_N -set_location_assignment PIN_AV11 -to ad9371_test ; ## D11 FMCA_HPC_LA05_P (DNI/NC) -set_location_assignment PIN_AN20 -to ad9371_reset_b ; ## H10 FMCA_HPC_LA04_P -set_location_assignment PIN_AP19 -to ad9371_gpint ; ## H11 FMCA_HPC_LA04_N - -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint - -# single ended default - -set_location_assignment PIN_AR9 -to ad9371_gpio[0] ; ## H19 FMCA_HPC_LA15_P -set_location_assignment PIN_AT9 -to ad9371_gpio[1] ; ## H20 FMCA_HPC_LA15_N -set_location_assignment PIN_AT13 -to ad9371_gpio[2] ; ## G18 FMCA_HPC_LA16_P -set_location_assignment PIN_AU13 -to ad9371_gpio[3] ; ## G19 FMCA_HPC_LA16_N -set_location_assignment PIN_AY10 -to ad9371_gpio[4] ; ## H25 FMCA_HPC_LA21_P -set_location_assignment PIN_AY11 -to ad9371_gpio[5] ; ## H26 FMCA_HPC_LA21_N -set_location_assignment PIN_AU21 -to ad9371_gpio[6] ; ## C22 FMCA_HPC_LA18_CC_P -set_location_assignment PIN_AV21 -to ad9371_gpio[7] ; ## C23 FMCA_HPC_LA18_CC_N -set_location_assignment PIN_AY12 -to ad9371_gpio[8] ; ## G25 FMCA_HPC_LA22_N (LVDS_1N) -set_location_assignment PIN_AU11 -to ad9371_gpio[9] ; ## H22 FMCA_HPC_LA19_P (LVDS_2P) -set_location_assignment PIN_AU12 -to ad9371_gpio[10] ; ## H23 FMCA_HPC_LA19_N (LVDS_2N) -set_location_assignment PIN_AU8 -to ad9371_gpio[11] ; ## G21 FMCA_HPC_LA20_P (LVDS_3P) -set_location_assignment PIN_AT8 -to ad9371_gpio[12] ; ## G22 FMCA_HPC_LA20_N (LVDS_3N) -set_location_assignment PIN_BA14 -to ad9371_gpio[13] ; ## G31 FMCA_HPC_LA29_N (LVDS_4N) -set_location_assignment PIN_BA15 -to ad9371_gpio[14] ; ## G30 FMCA_HPC_LA29_P (LVDS_4P) -set_location_assignment PIN_AW12 -to ad9371_gpio[15] ; ## G24 FMCA_HPC_LA22_P (LVDS_1P) -set_location_assignment PIN_AP16 -to ad9371_gpio[16] ; ## G16 FMCA_HPC_LA12_N (LVDS_5N) -set_location_assignment PIN_AR16 -to ad9371_gpio[17] ; ## G15 FMCA_HPC_LA12_P (LVDS_5P) -set_location_assignment PIN_AW11 -to ad9371_gpio[18] ; ## D12 FMCA_HPC_LA05_N - -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18] - -## improve timing - there are occasional timing failure with a small negative slack -# at no-MMU configuration -set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" - -execute_flow -compile diff --git a/projects/adrv9371x/a10gx/system_qsys.tcl b/projects/adrv9371x/a10gx/system_qsys.tcl deleted file mode 100644 index 4b2c87534..000000000 --- a/projects/adrv9371x/a10gx/system_qsys.tcl +++ /dev/null @@ -1,22 +0,0 @@ - -set dac_fifo_address_width 10 - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl -source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl - -if [info exists ad_project_dir] { - source ../../common/adrv9371x_qsys.tcl -} else { - source ../common/adrv9371x_qsys.tcl -} - -#system ID - -set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} -set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} - -set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" - -sysid_gen_sys_init_file; - diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v deleted file mode 100644 index 8b1f65f1e..000000000 --- a/projects/adrv9371x/a10gx/system_top.v +++ /dev/null @@ -1,242 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - input sys_resetn, - - // ddr3 - - output ddr3_clk_p, - output ddr3_clk_n, - output [ 14:0] ddr3_a, - output [ 2:0] ddr3_ba, - output ddr3_cke, - output ddr3_cs_n, - output ddr3_odt, - output ddr3_reset_n, - output ddr3_we_n, - output ddr3_ras_n, - output ddr3_cas_n, - inout [ 7:0] ddr3_dqs_p, - inout [ 7:0] ddr3_dqs_n, - inout [ 63:0] ddr3_dq, - output [ 7:0] ddr3_dm, - input ddr3_rzq, - input ddr3_ref_clk, - - // ethernet - - input eth_ref_clk, - input eth_rxd, - output eth_txd, - output eth_mdc, - inout eth_mdio, - output eth_resetn, - input eth_intn, - - // board gpio - - input [ 10:0] gpio_bd_i, - output [ 15:0] gpio_bd_o, - - // flash - - output flash_oen, - output [ 1:0] flash_cen, - output [ 27:0] flash_addr, - inout [ 31:0] flash_data, - output flash_wen, - output flash_advn, - output flash_clk, - output flash_resetn, - - // lane interface - - input ref_clk0, - input ref_clk1, - input [ 3:0] rx_serial_data, - output [ 3:0] tx_serial_data, - output rx_sync, - output rx_os_sync, - input tx_sync, - input sysref, - - output ad9528_reset_b, - output ad9528_sysref_req, - output ad9371_tx1_enable, - output ad9371_tx2_enable, - output ad9371_rx1_enable, - output ad9371_rx2_enable, - output ad9371_test, - output ad9371_reset_b, - input ad9371_gpint, - - inout [ 18:0] ad9371_gpio, - - output spi_csn_ad9528, - output spi_csn_ad9371, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire eth_reset; - wire eth_mdio_i; - wire eth_mdio_o; - wire eth_mdio_t; - wire [ 63:0] gpio_i; - wire [ 63:0] gpio_o; - wire [ 7:0] spi_csn_s; - wire dac_fifo_bypass; - wire [23:0] flash_addr_raw; - - // assignments - - assign spi_csn_ad9528 = spi_csn_s[0]; - assign spi_csn_ad9371 = spi_csn_s[1]; - - // gpio (ad9371) - - assign gpio_i[63:61] = gpio_o[63:61]; - - assign dac_fifo_bypass = gpio_o[60]; - assign gpio_i[60:60] = gpio_o[60:60]; - - assign ad9528_reset_b = gpio_o[59]; - assign ad9528_sysref_req = gpio_o[58]; - assign ad9371_tx1_enable = gpio_o[57]; - assign ad9371_tx2_enable = gpio_o[56]; - assign ad9371_rx1_enable = gpio_o[55]; - assign ad9371_rx2_enable = gpio_o[54]; - assign ad9371_test = gpio_o[53]; - assign ad9371_reset_b = gpio_o[52]; - assign gpio_i[59:52] = gpio_o[59:52]; - - assign gpio_i[51:51] = ad9371_gpint; - - assign gpio_i[50:32] = gpio_o[50:32]; - - // board stuff - - assign eth_resetn = ~eth_reset; - assign eth_mdio_i = eth_mdio; - assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; - - assign ddr3_a[14:12] = 3'd0; - - assign gpio_i[31:27] = gpio_o[31:27]; - assign gpio_i[26:16] = gpio_bd_i; - assign gpio_i[15: 0] = gpio_o[15: 0]; - - assign gpio_bd_o = gpio_o[15:0]; - - // User code space at offset 0x0930_0000 per Intel's Board Update Portal - // reference design used to program flash - - assign flash_addr = flash_addr_raw + 28'h9300000; - - // Common Flash interface assignments - - assign flash_resetn = 1'b1; - assign flash_advn = 1'b0; - assign flash_clk = 1'b0; - assign flash_cen[1] = flash_cen[0]; - - system_bd i_system_bd ( - .ad9371_gpio_export (ad9371_gpio), - .sys_clk_clk (sys_clk), - .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .sys_ethernet_mdio_mdc (eth_mdc), - .sys_ethernet_mdio_mdio_in (eth_mdio_i), - .sys_ethernet_mdio_mdio_out (eth_mdio_o), - .sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .sys_ethernet_ref_clk_clk (eth_ref_clk), - .sys_ethernet_reset_reset (eth_reset), - .sys_ethernet_sgmii_rxp_0 (eth_rxd), - .sys_ethernet_sgmii_txp_0 (eth_txd), - .sys_gpio_bd_in_port (gpio_i[31:0]), - .sys_gpio_bd_out_port (gpio_o[31:0]), - .sys_gpio_in_export (gpio_i[63:32]), - .sys_gpio_out_export (gpio_o[63:32]), - .pr_rom_data_nc_rom_data('h0), - .sys_rst_reset_n (sys_resetn), - .sys_spi_MISO (spi_miso), - .sys_spi_MOSI (spi_mosi), - .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n (spi_csn_s), - .tx_serial_data_tx_serial_data (tx_serial_data), - .tx_fifo_bypass_bypass (dac_fifo_bypass), - .tx_ref_clk_clk (ref_clk1), - .tx_sync_export (tx_sync), - .tx_sysref_export (sysref), - .rx_serial_data_rx_serial_data (rx_serial_data[1:0]), - .rx_os_serial_data_rx_serial_data (rx_serial_data[3:2]), - .rx_os_ref_clk_clk (ref_clk1), - .rx_os_sync_export (rx_os_sync), - .rx_os_sysref_export (sysref), - .rx_ref_clk_clk (ref_clk1), - .rx_sync_export (rx_sync), - .rx_sysref_export (sysref), - .sys_flash_tcm_address_out (flash_addr_raw), - .sys_flash_tcm_read_n_out (flash_oen), - .sys_flash_tcm_write_n_out (flash_wen), - .sys_flash_tcm_data_out (flash_data), - .sys_flash_tcm_chipselect_n_out (flash_cen[0])); - -endmodule diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile deleted file mode 100644 index e197d1898..000000000 --- a/projects/daq2/a10gx/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := daq2_a10gx - -M_DEPS += ../common/daq2_qsys.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../daq2/common/daq2_spi.v -M_DEPS += ../../common/intel/dacfifo_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += intel/adi_jesd204 -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac -LIB_DEPS += sysid_rom -LIB_DEPS += util_adcfifo -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 - -include ../../scripts/project-intel.mk diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc deleted file mode 100644 index bad773591..000000000 --- a/projects/daq2/a10gx/system_constr.sdc +++ /dev/null @@ -1,12 +0,0 @@ - -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}] -create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}] - -derive_pll_clocks -derive_clock_uncertainty - -set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] - -set_false_path -from * -to [get_ports {flash_resetn}] - diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl deleted file mode 100644 index 3ef7f6d47..000000000 --- a/projects/daq2/a10gx/system_project.tcl +++ /dev/null @@ -1,99 +0,0 @@ -source ../../../scripts/adi_env.tcl -source ../../scripts/adi_project_intel.tcl - -adi_project daq2_a10gx - -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl - -# files - -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/daq2/common/daq2_spi.v - -# lane interface - -set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P -set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N -set_location_assignment PIN_AV5 -to rx_serial_data[0] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_serial_data[0](n)"; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_AW7 -to rx_serial_data[1] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_serial_data[1](n)"; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_AY5 -to rx_serial_data[2] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_serial_data[2](n)"; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_BA7 -to rx_serial_data[3] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_serial_data[3](n)"; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P -set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N -set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P -set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N -set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_BC3 -to tx_serial_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0]) -set_location_assignment PIN_BC4 -to "tx_serial_data[0](n)"; ## A31 FMCA_DP3_C2M_N (tx_data_n[0]) -set_location_assignment PIN_BC7 -to tx_serial_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3]) -set_location_assignment PIN_BC8 -to "tx_serial_data[1](n)"; ## C03 FMCA_DP0_C2M_N (tx_data_n[3]) -set_location_assignment PIN_BB5 -to tx_serial_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1]) -set_location_assignment PIN_BB6 -to "tx_serial_data[2](n)"; ## A27 FMCA_DP2_C2M_N (tx_data_n[1]) -set_location_assignment PIN_BD5 -to tx_serial_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2]) -set_location_assignment PIN_BD6 -to "tx_serial_data[3](n)"; ## A23 FMCA_DP1_C2M_N (tx_data_n[2]) -set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P -set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N -set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P -set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N - -set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_clk -set_instance_assignment -name IO_STANDARD LVDS -to "rx_ref_clk(n)" -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync -set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync(n)" -set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref -set_instance_assignment -name IO_STANDARD LVDS -to "rx_sysref(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref - -set_instance_assignment -name IO_STANDARD LVDS -to tx_ref_clk -set_instance_assignment -name IO_STANDARD LVDS -to "tx_ref_clk(n)" -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data -set_instance_assignment -name IO_STANDARD LVDS -to tx_sync -set_instance_assignment -name IO_STANDARD LVDS -to "tx_sync(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync -set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref -set_instance_assignment -name IO_STANDARD LVDS -to "tx_sysref(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref - -# Merge RX and TX into single transceiver -for {set i 0} {$i < 4} {incr i} { - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] - set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] -} - -# gpio - -set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P -set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N -set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N -set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P -set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P -set_location_assignment PIN_AP17 -to clkd_status[1] ; ## D18 FMCA_LA13_N -set_location_assignment PIN_AR17 -to clkd_status[0] ; ## D17 FMCA_LA13_P -set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P -set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N -set_location_assignment PIN_AT15 -to dac_reset ; ## C15 FMCA_LA10_N -set_location_assignment PIN_AP18 -to clkd_sync ; ## G12 FMCA_LA08_P - -set_instance_assignment -name IO_STANDARD LVDS -to trig - -# spi - -set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P -set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P -set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N -set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N -set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P -set_location_assignment PIN_AN19 -to spi_dir ; ## G13 FMCA_LA08_N - -## improve timing - there are occasional timing failure with a small negative slack -# at no-MMU configuration -set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" - -execute_flow -compile diff --git a/projects/daq2/a10gx/system_qsys.tcl b/projects/daq2/a10gx/system_qsys.tcl deleted file mode 100644 index 48235c30b..000000000 --- a/projects/daq2/a10gx/system_qsys.tcl +++ /dev/null @@ -1,21 +0,0 @@ -set dac_fifo_address_width 10 - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl -source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl - -if [info exists ad_project_dir] { - source ../../common/daq2_qsys.tcl -} else { - source ../common/daq2_qsys.tcl -} - -#system ID - -set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} -set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} - -set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" - -sysid_gen_sys_init_file; - diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v deleted file mode 100644 index ef2305286..000000000 --- a/projects/daq2/a10gx/system_top.v +++ /dev/null @@ -1,252 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - input sys_resetn, - - // ddr3 - - output ddr3_clk_p, - output ddr3_clk_n, - output [ 14:0] ddr3_a, - output [ 2:0] ddr3_ba, - output ddr3_cke, - output ddr3_cs_n, - output ddr3_odt, - output ddr3_reset_n, - output ddr3_we_n, - output ddr3_ras_n, - output ddr3_cas_n, - inout [ 7:0] ddr3_dqs_p, - inout [ 7:0] ddr3_dqs_n, - inout [ 63:0] ddr3_dq, - output [ 7:0] ddr3_dm, - input ddr3_rzq, - input ddr3_ref_clk, - - // ethernet - - input eth_ref_clk, - input eth_rxd, - output eth_txd, - output eth_mdc, - inout eth_mdio, - output eth_resetn, - input eth_intn, - - // board gpio - - input [ 10:0] gpio_bd_i, - output [ 15:0] gpio_bd_o, - - // flash - - output flash_oen, - output [ 1:0] flash_cen, - output [ 27:0] flash_addr, // drop A0 & A1 for 32 bit data bus - inout [ 31:0] flash_data, - output flash_wen, - output flash_advn, - output flash_clk, - output flash_resetn, - - // lane interface - - input rx_ref_clk, - input rx_sysref, - output rx_sync, - input [ 3:0] rx_serial_data, - input tx_ref_clk, - input tx_sysref, - input tx_sync, - output [ 3:0] tx_serial_data, - - // gpio - - input trig, - input adc_fdb, - input adc_fda, - input dac_irq, - input [ 1:0] clkd_status, - output adc_pd, - output dac_txen, - output dac_reset, - output clkd_sync, - - // spi - - output spi_csn_clk, - output spi_csn_dac, - output spi_csn_adc, - output spi_clk, - inout spi_sdio, - output spi_dir -); - - // internal signals - - wire eth_reset; - wire eth_mdio_i; - wire eth_mdio_o; - wire eth_mdio_t; - wire [ 63:0] gpio_i; - wire [ 63:0] gpio_o; - wire spi_miso_s; - wire spi_mosi_s; - wire [ 7:0] spi_csn_s; - wire dac_fifo_bypass; - - // User code space at offset 0x0930_0000 per Intel's Board Update Portal - // reference design used to program flash - - wire [23:0] flash_addr_raw; - assign flash_addr = flash_addr_raw + 28'h9300000; - - // daq2 - - assign spi_csn_adc = spi_csn_s[2]; - assign spi_csn_dac = spi_csn_s[1]; - assign spi_csn_clk = spi_csn_s[0]; - - daq2_spi i_daq2_spi ( - .spi_csn (spi_csn_s[2:0]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi_s), - .spi_miso (spi_miso_s), - .spi_sdio (spi_sdio), - .spi_dir (spi_dir)); - - // gpio in & out are separate cores - - assign gpio_i[63:44] = gpio_o[63:44]; - assign dac_fifo_bypass = gpio_o[44]; - assign gpio_i[43:43] = trig; - - assign gpio_i[42:40] = gpio_o[42:40]; - assign adc_pd = gpio_o[42]; - assign dac_txen = gpio_o[41]; - assign dac_reset = gpio_o[40]; - - assign gpio_i[39:39] = gpio_o[39:39]; - - assign gpio_i[38:38] = gpio_o[38:38]; - assign clkd_sync = gpio_o[38]; - - assign gpio_i[37:37] = gpio_o[37:37]; - assign gpio_i[36:36] = adc_fdb; - assign gpio_i[35:35] = adc_fda; - assign gpio_i[34:34] = dac_irq; - assign gpio_i[33:32] = clkd_status; - - // board stuff - - assign eth_resetn = ~eth_reset; - assign eth_mdio_i = eth_mdio; - assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; - - assign ddr3_a[14:12] = 3'd0; - - assign gpio_i[31:27] = gpio_o[31:27]; - assign gpio_i[26:16] = gpio_bd_i; - assign gpio_i[15: 0] = gpio_o[15: 0]; - - assign gpio_bd_o = gpio_o[15:0]; - - // Common Flash interface assignments - - assign flash_resetn = 1'b1; // user_resetn; flash ready after FPGA is configured, reset during configuration - assign flash_advn = 1'b0; - assign flash_clk = 1'b0; - assign flash_cen[1] = flash_cen[0]; // select both flash devices for double-wide 32 bit data width - - system_bd i_system_bd ( - .rx_serial_data_rx_serial_data (rx_serial_data), - .rx_ref_clk_clk (rx_ref_clk), - .rx_sync_export (rx_sync), - .rx_sysref_export (rx_sysref), - .sys_clk_clk (sys_clk), - .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .sys_ethernet_mdio_mdc (eth_mdc), - .sys_ethernet_mdio_mdio_in (eth_mdio_i), - .sys_ethernet_mdio_mdio_out (eth_mdio_o), - .sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .sys_ethernet_ref_clk_clk (eth_ref_clk), - .sys_ethernet_reset_reset (eth_reset), - .sys_ethernet_sgmii_rxp_0 (eth_rxd), - .sys_ethernet_sgmii_txp_0 (eth_txd), - .sys_gpio_bd_in_port (gpio_i[31:0]), - .sys_gpio_bd_out_port (gpio_o[31:0]), - .sys_gpio_in_export (gpio_i[63:32]), - .sys_gpio_out_export (gpio_o[63:32]), - .pr_rom_data_nc_rom_data('h0), - .sys_rst_reset_n (sys_resetn), - .sys_spi_MISO (spi_miso_s), - .sys_spi_MOSI (spi_mosi_s), - .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n (spi_csn_s), - .tx_serial_data_tx_serial_data (tx_serial_data), - .tx_fifo_bypass_bypass (dac_fifo_bypass), - .tx_ref_clk_clk (tx_ref_clk), - .tx_sync_export (tx_sync), - .tx_sysref_export (tx_sysref), - .sys_flash_tcm_address_out (flash_addr_raw), - .sys_flash_tcm_read_n_out (flash_oen), - .sys_flash_tcm_write_n_out (flash_wen), - .sys_flash_tcm_data_out (flash_data), - .sys_flash_tcm_chipselect_n_out (flash_cen[0])); - -endmodule diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile deleted file mode 100644 index 70e1a7d9a..000000000 --- a/projects/daq3/a10gx/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := daq3_a10gx - -M_DEPS += ../common/daq3_qsys.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../daq3/common/daq3_spi.v -M_DEPS += ../../common/intel/dacfifo_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl -M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += intel/adi_jesd204 -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac -LIB_DEPS += sysid_rom -LIB_DEPS += util_adcfifo -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 - -include ../../scripts/project-intel.mk diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc deleted file mode 100644 index aae81d787..000000000 --- a/projects/daq3/a10gx/system_constr.sdc +++ /dev/null @@ -1,14 +0,0 @@ - -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "1.621 ns" -name rx_ref_clk [get_ports {rx_ref_clk}] -create_clock -period "1.621 ns" -name tx_ref_clk [get_ports {tx_ref_clk}] - -derive_pll_clocks -derive_clock_uncertainty - -set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] - -# flash interface - -set_false_path -from * -to [get_ports {flash_resetn}] - diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl deleted file mode 100644 index 0c8309ae6..000000000 --- a/projects/daq3/a10gx/system_project.tcl +++ /dev/null @@ -1,101 +0,0 @@ -source ../../../scripts/adi_env.tcl -source ../../scripts/adi_project_intel.tcl - -adi_project daq3_a10gx - -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl - -# files - -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/daq3/common/daq3_spi.v - -# lane interface - -set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P -set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N -set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P -set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N -set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P -set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N -set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0]) -set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0]) -set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3]) -set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3]) -set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1]) -set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1]) -set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2]) -set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2]) -set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P -set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N -set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P -set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N - -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_ref_clk -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_ref_clk -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data - -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] -set_instance_assignment -name IO_STANDARD LVDS -to rx_sync -set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] -set_instance_assignment -name IO_STANDARD LVDS -to tx_sync -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync -set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref - -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] - -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] - -# gpio - -set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P -set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N -set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N -set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P -set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P -set_location_assignment PIN_AN19 -to clkd_status[1] ; ## G13 FMCA_LA08_N -set_location_assignment PIN_AP18 -to clkd_status[0] ; ## G12 FMCA_LA08_P -set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P -set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N -set_location_assignment PIN_AR17 -to sysref ; ## D17 FMCA_LA13_P -set_location_assignment PIN_AP17 -to "sysref(n)" ; ## D18 FMCA_LA13_N - -set_instance_assignment -name IO_STANDARD LVDS -to trig -set_instance_assignment -name IO_STANDARD LVDS -to sysref - -# spi - -set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P -set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P -set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N -set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N -set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P -set_location_assignment PIN_AW14 -to spi_dir ; ## C11 FMCA_LA06_N - -execute_flow -compile - diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl deleted file mode 100644 index 70c0b0299..000000000 --- a/projects/daq3/a10gx/system_qsys.tcl +++ /dev/null @@ -1,20 +0,0 @@ -set dac_fifo_address_width 10 - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl -source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl - -if [info exists ad_project_dir] { - source ../../common/daq3_qsys.tcl -} else { - source ../common/daq3_qsys.tcl -} - -#system ID -set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} -set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} - -set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" - -sysid_gen_sys_init_file; - diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v deleted file mode 100644 index d2ffa1109..000000000 --- a/projects/daq3/a10gx/system_top.v +++ /dev/null @@ -1,245 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - input sys_resetn, - - // ddr3 - - output ddr3_clk_p, - output ddr3_clk_n, - output [ 14:0] ddr3_a, - output [ 2:0] ddr3_ba, - output ddr3_cke, - output ddr3_cs_n, - output ddr3_odt, - output ddr3_reset_n, - output ddr3_we_n, - output ddr3_ras_n, - output ddr3_cas_n, - inout [ 7:0] ddr3_dqs_p, - inout [ 7:0] ddr3_dqs_n, - inout [ 63:0] ddr3_dq, - output [ 7:0] ddr3_dm, - input ddr3_rzq, - input ddr3_ref_clk, - - // ethernet - - input eth_ref_clk, - input eth_rxd, - output eth_txd, - output eth_mdc, - inout eth_mdio, - output eth_resetn, - input eth_intn, - - // board gpio - - input [ 10:0] gpio_bd_i, - output [ 15:0] gpio_bd_o, - - // flash - - output flash_oen, - output [ 1:0] flash_cen, - output [ 27:0] flash_addr, - inout [ 31:0] flash_data, - output flash_wen, - output flash_advn, - output flash_clk, - output flash_resetn, - - // lane interface - - input rx_ref_clk, - input rx_sysref, - output rx_sync, - input [ 3:0] rx_data, - input tx_ref_clk, - input tx_sysref, - input tx_sync, - output [ 3:0] tx_data, - - // gpio - - input trig, - input adc_fdb, - input adc_fda, - input dac_irq, - input [ 1:0] clkd_status, - output adc_pd, - output dac_txen, - output sysref, - - // spi - - output spi_csn_clk, - output spi_csn_dac, - output spi_csn_adc, - output spi_clk, - inout spi_sdio, - output spi_dir -); - - // internal signals - - wire eth_reset; - wire eth_mdio_i; - wire eth_mdio_o; - wire eth_mdio_t; - wire [ 63:0] gpio_i; - wire [ 63:0] gpio_o; - wire spi_miso_s; - wire spi_mosi_s; - wire [ 7:0] spi_csn_s; - wire dac_fifo_bypass; - wire [ 23:0] flash_addr_raw; - - // daq3 - - assign spi_csn_adc = spi_csn_s[2]; - assign spi_csn_dac = spi_csn_s[1]; - assign spi_csn_clk = spi_csn_s[0]; - - daq3_spi i_daq3_spi ( - .spi_csn (spi_csn_s[2:0]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi_s), - .spi_miso (spi_miso_s), - .spi_sdio (spi_sdio), - .spi_dir (spi_dir)); - - // gpio in & out are separate cores - - assign gpio_i[63:40] = gpio_o[63:40]; - assign dac_fifo_bypass = gpio_o[41]; - assign sysref = gpio_o[40]; - assign gpio_i[39:39] = trig; - - assign gpio_i[38:37] = gpio_o[38:37]; - assign adc_pd = gpio_o[38]; - assign dac_txen = gpio_o[37]; - - assign gpio_i[36:36] = adc_fdb; - assign gpio_i[35:35] = adc_fda; - assign gpio_i[34:34] = dac_irq; - assign gpio_i[33:32] = clkd_status; - - // board stuff - - assign eth_resetn = ~eth_reset; - assign eth_mdio_i = eth_mdio; - assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; - - assign ddr3_a[14:12] = 3'd0; - - assign gpio_i[31:27] = gpio_o[31:27]; - assign gpio_i[26:16] = gpio_bd_i; - assign gpio_i[15: 0] = gpio_o[15: 0]; - - assign gpio_bd_o = gpio_o[15:0]; - - // User code space at offset 0x0930_0000 per Intel's Board Update Portal - // reference design used to program flash - - assign flash_addr = flash_addr_raw + 28'h9300000; - - // Common Flash interface assignments - - assign flash_resetn = 1'b1; // user_resetn; flash ready after FPGA is configured, reset during configuration - assign flash_advn = 1'b0; - assign flash_clk = 1'b0; - assign flash_cen[1] = flash_cen[0]; // select both flash devices for double-wide 32 bit data width - - system_bd i_system_bd ( - .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .sys_ethernet_mdio_mdc (eth_mdc), - .sys_ethernet_mdio_mdio_in (eth_mdio_i), - .sys_ethernet_mdio_mdio_out (eth_mdio_o), - .sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .sys_ethernet_ref_clk_clk (eth_ref_clk), - .sys_ethernet_reset_reset (eth_reset), - .sys_ethernet_sgmii_rxp_0 (eth_rxd), - .sys_ethernet_sgmii_txp_0 (eth_txd), - .sys_gpio_in_export (gpio_i[63:32]), - .sys_gpio_out_export (gpio_o[63:32]), - .sys_gpio_bd_in_port (gpio_i[31:0]), - .sys_gpio_bd_out_port (gpio_o[31:0]), - .pr_rom_data_nc_rom_data('h0), - .sys_spi_MISO (spi_miso_s), - .sys_spi_MOSI (spi_mosi_s), - .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n (spi_csn_s), - .rx_serial_data_rx_serial_data (rx_data), - .rx_ref_clk_clk (rx_ref_clk), - .rx_sync_export (rx_sync), - .rx_sysref_export (rx_sysref), - .tx_serial_data_tx_serial_data (tx_data), - .tx_fifo_bypass_bypass (dac_fifo_bypass), - .tx_ref_clk_clk (tx_ref_clk), - .tx_sync_export (tx_sync), - .tx_sysref_export (tx_sysref), - .sys_clk_clk (sys_clk), - .sys_rst_reset_n (sys_resetn), - .sys_flash_tcm_address_out (flash_addr_raw), - .sys_flash_tcm_read_n_out (flash_oen), - .sys_flash_tcm_write_n_out (flash_wen), - .sys_flash_tcm_data_out (flash_data), - .sys_flash_tcm_chipselect_n_out (flash_cen[0])); - -endmodule diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl deleted file mode 100644 index b57ff229e..000000000 --- a/projects/daq3/common/daq3_qsys.tcl +++ /dev/null @@ -1,232 +0,0 @@ -# JESD204B attributes - -set RX_NUM_OF_LANES 4 ; # L -set RX_NUM_OF_CONVERTERS 2 ; # M -set RX_SAMPLES_PER_FRAME 1 ; # S -set RX_SAMPLE_WIDTH 16 ; # N/NP - -set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] - -set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL] - -set TX_NUM_OF_LANES 4 ; # L -set TX_NUM_OF_CONVERTERS 2 ; # M -set TX_SAMPLES_PER_FRAME 1 ; # S -set TX_SAMPLE_WIDTH 16 ; # N/NP - -set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] - -set dac_fifo_name avl_ad9152_fifo -set dac_data_width 128 - -# ad9152-xcvr - -add_instance ad9152_jesd204 adi_jesd204 -set_instance_parameter_value ad9152_jesd204 {ID} {0} -set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1} -set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3} -set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665} -set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES -set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2} - -add_connection sys_clk.clk ad9152_jesd204.sys_clk -add_connection sys_clk.clk_reset ad9152_jesd204.sys_resetn -add_interface tx_ref_clk clock sink -set_interface_property tx_ref_clk EXPORT_OF ad9152_jesd204.ref_clk -add_interface tx_serial_data conduit end -set_interface_property tx_serial_data EXPORT_OF ad9152_jesd204.serial_data -add_interface tx_sysref conduit end -set_interface_property tx_sysref EXPORT_OF ad9152_jesd204.sysref -add_interface tx_sync conduit end -set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync - -# ad9152-core - -add_instance axi_ad9152_tpl ad_ip_jesd204_tpl_dac -set_instance_parameter_value axi_ad9152_tpl {ID} {0} -set_instance_parameter_value axi_ad9152_tpl {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS -set_instance_parameter_value axi_ad9152_tpl {NUM_LANES} $TX_NUM_OF_LANES -set_instance_parameter_value axi_ad9152_tpl {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH -set_instance_parameter_value axi_ad9152_tpl {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH - -add_connection ad9152_jesd204.link_clk axi_ad9152_tpl.link_clk -add_connection axi_ad9152_tpl.link_data ad9152_jesd204.link_data -add_connection sys_clk.clk_reset axi_ad9152_tpl.s_axi_reset -add_connection sys_clk.clk axi_ad9152_tpl.s_axi_clock - -# ad9152-unpack - -add_instance util_ad9152_upack util_upack2 -set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS -set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL -set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} $TX_SAMPLE_WIDTH -set_instance_parameter_value util_ad9152_upack {INTERFACE_TYPE} {1} - -add_connection ad9152_jesd204.link_clk util_ad9152_upack.clk -add_connection ad9152_jesd204.link_reset util_ad9152_upack.reset -add_connection axi_ad9152_tpl.dac_ch_0 util_ad9152_upack.dac_ch_0 -add_connection axi_ad9152_tpl.dac_ch_1 util_ad9152_upack.dac_ch_1 - -# dac fifo - -ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width - -add_interface tx_fifo_bypass conduit end -set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass - -add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk -add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst -add_connection util_ad9152_upack.if_packed_fifo_rd_en avl_ad9152_fifo.if_dac_valid -add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_packed_fifo_rd_data -add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_tpl.if_dac_dunf - -# ad9152-dma - -add_instance axi_ad9152_dma axi_dmac -set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128} -set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} $dac_data_width -set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_ad9152_dma {CYCLIC} {1} -set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1} -set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0} -set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16} -set_instance_parameter_value axi_ad9152_dma {HAS_AXIS_TLAST} {1} - -add_connection sys_clk.clk avl_ad9152_fifo.if_dma_clk -add_connection sys_clk.clk_reset avl_ad9152_fifo.if_dma_rst -add_connection sys_clk.clk axi_ad9152_dma.if_m_axis_aclk -add_connection axi_ad9152_dma.m_axis avl_ad9152_fifo.s_axis -add_connection axi_ad9152_dma.if_m_axis_xfer_req avl_ad9152_fifo.if_dma_xfer_req -add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset -add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9152_dma.m_src_axi_reset -add_connection sys_clk.clk axi_ad9152_dma.m_src_axi_clock - -# ad9680-xcvr - -add_instance ad9680_jesd204 adi_jesd204 -set_instance_parameter_value ad9680_jesd204 {ID} {1} -set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0} -set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {12333.3} -set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {616.665} -set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4} -set_instance_parameter_value ad9680_jesd204 {INPUT_PIPELINE_STAGES} {1} - -add_connection sys_clk.clk ad9680_jesd204.sys_clk -add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn -add_interface rx_ref_clk clock sink -set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk -add_interface rx_serial_data conduit end -set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data -add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref -add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync - -# ad9680 - -add_instance axi_ad9680_tpl ad_ip_jesd204_tpl_adc -set_instance_parameter_value axi_ad9680_tpl {ID} {0} -set_instance_parameter_value axi_ad9680_tpl {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS -set_instance_parameter_value axi_ad9680_tpl {NUM_LANES} $RX_NUM_OF_LANES -set_instance_parameter_value axi_ad9680_tpl {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH -set_instance_parameter_value axi_ad9680_tpl {CONVERTER_RESOLUTION} {14} -set_instance_parameter_value axi_ad9680_tpl {TWOS_COMPLEMENT} {0} - -add_connection ad9680_jesd204.link_clk axi_ad9680_tpl.link_clk -add_connection ad9680_jesd204.link_sof axi_ad9680_tpl.if_link_sof -add_connection ad9680_jesd204.link_data axi_ad9680_tpl.link_data -add_connection sys_clk.clk_reset axi_ad9680_tpl.s_axi_reset -add_connection sys_clk.clk axi_ad9680_tpl.s_axi_clock - -# ad9680-pack - -add_instance util_ad9680_cpack util_cpack2 -set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS -set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} $RX_NUM_OF_LANES -set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH - -add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk -add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset -add_connection axi_ad9680_tpl.adc_ch_0 util_ad9680_cpack.adc_ch_0 -add_connection axi_ad9680_tpl.adc_ch_1 util_ad9680_cpack.adc_ch_1 - -# ad9680-fifo - -add_instance ad9680_adcfifo util_adcfifo -set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} $adc_data_width -set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} $adc_data_width -set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16} - -add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst -add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk -add_connection util_ad9680_cpack.if_packed_fifo_wr_en ad9680_adcfifo.if_adc_wr -add_connection util_ad9680_cpack.if_packed_fifo_wr_data ad9680_adcfifo.if_adc_wdata -add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk - -# ad9680-dma - -add_instance axi_ad9680_dma axi_dmac -set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} $adc_data_width -set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0} -set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1} - -add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk -add_connection ad9680_adcfifo.m_axis axi_ad9680_dma.s_axis -add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req -add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_tpl.if_adc_dovf -add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset -add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset -add_connection sys_clk.clk axi_ad9680_dma.m_dest_axi_clock - -# reconfig sharing - -for {set i 0} {$i < 4} {incr i} { - add_instance avl_adxcfg_${i} avl_adxcfg - add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk - add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n - add_connection avl_adxcfg_${i}.rcfg_m0 ad9152_jesd204.phy_reconfig_${i} - add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i} -} - -# addresses - -ad_cpu_interconnect 0x00400000 ad9152_jesd204.link_reconfig -ad_cpu_interconnect 0x00424000 ad9152_jesd204.link_management -ad_cpu_interconnect 0x00425000 ad9152_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00426000 ad9152_jesd204.lane_pll_reconfig -ad_cpu_interconnect 0x00428000 avl_adxcfg_0.rcfg_s0 -ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0 -ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0 -ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0 -ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi -ad_cpu_interconnect 0x00434000 axi_ad9152_tpl.s_axi - -ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig -ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management -ad_cpu_interconnect 0x00445000 ad9680_jesd204.link_pll_reconfig -ad_cpu_interconnect 0x00448000 avl_adxcfg_0.rcfg_s1 -ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1 -ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1 -ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1 -ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi -ad_cpu_interconnect 0x00450000 axi_ad9680_tpl.s_axi - -# dma interconnects - -ad_dma_interconnect axi_ad9152_dma.m_src_axi -ad_dma_interconnect axi_ad9680_dma.m_dest_axi - -# interrupts - -ad_cpu_interrupt 8 ad9680_jesd204.interrupt -ad_cpu_interrupt 9 ad9152_jesd204.interrupt -ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender -ad_cpu_interrupt 11 axi_ad9152_dma.interrupt_sender