From 302e59e10955d9ee02facb88178ac51cdc7dfc94 Mon Sep 17 00:00:00 2001 From: Filip Gherman Date: Mon, 9 May 2022 17:58:58 +0300 Subject: [PATCH] data_offload_constr.ttcl: Fix false_paths for i_sync_src_transfer_length registers --- library/data_offload/data_offload_constr.ttcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/data_offload/data_offload_constr.ttcl b/library/data_offload/data_offload_constr.ttcl index 97d4a1814..a0f083c40 100644 --- a/library/data_offload/data_offload_constr.ttcl +++ b/library/data_offload/data_offload_constr.ttcl @@ -21,6 +21,8 @@ set_property ASYNC_REG TRUE \ -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_wr_sync/cdc_sync_stage1_reg[*]/D}] <: } :> +<: } :> + set_false_path \ -from [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/cdc_hold_reg[*]}] \ -to [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_data_reg[*]}] @@ -33,8 +35,6 @@ set_false_path \ -from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_toggle_d1_reg/C}] \ -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_in/cdc_sync_stage1_reg[*]/D}] -<: } :> - ## For TX in case of BRAMs <: if { $tx_enable } { :>