From 3041e77659c066241cca9803c7c91463bdbbc9e3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 19 Jan 2021 15:32:48 +0000 Subject: [PATCH] ad40xx/zed: Update constraints --- projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc | 12 ++++++++---- projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc b/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc index 288fa93bb..ba582677c 100644 --- a/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc +++ b/projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc @@ -10,8 +10,12 @@ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_p ## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the # execution's shift register, because we load new data into the shift register -# in every DATA_WIDTH's x 2 cycle. (worst case scenario) -# Set a multi-cycle delay of 2 spi_clk cycle, slightly over constraining the path. -set_multicycle_path 2 -setup -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/fifo.async_clocks.i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] -set_multicycle_path 1 -hold -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/fifo.async_clocks.i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] +# in every DATA_WIDTH's x 8 cycle. (worst case scenario) +# Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path. + +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] + +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] diff --git a/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc b/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc index 936cfe01f..874188dbf 100644 --- a/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc +++ b/projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc @@ -8,8 +8,12 @@ set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports adaq400x_sp ## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the # execution's shift register, because we load new data into the shift register -# in every DATA_WIDTH's x 2 cycle. (worst case scenario) -# Set a multi-cycle delay of 2 spi_clk cycle, slightly over constraining the path. -set_multicycle_path 2 -setup -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] -set_multicycle_path 1 -hold -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] +# in every DATA_WIDTH's x 8 cycle. (worst case scenario) +# Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path. + +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks clk_fpga_2] + +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks clk_fpga_2]