axi_tdd: Add standalone axi_tdd IP core
This commit adds a standalone TDD IP core based on the existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge. Signed-off-by: David Winter <david.winter@analog.com>main
David Winter
Laszlo Nagy
parent
20161cf458
commit
30cc7d7420
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@ -56,6 +56,7 @@ clean:
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$(MAKE) -C axi_spdif_rx clean
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$(MAKE) -C axi_spdif_rx clean
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$(MAKE) -C axi_spdif_tx clean
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$(MAKE) -C axi_spdif_tx clean
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$(MAKE) -C axi_sysid clean
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$(MAKE) -C axi_sysid clean
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$(MAKE) -C axi_tdd clean
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$(MAKE) -C axi_usb_fx3 clean
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$(MAKE) -C axi_usb_fx3 clean
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$(MAKE) -C cn0363/cn0363_dma_sequencer clean
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$(MAKE) -C cn0363/cn0363_dma_sequencer clean
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$(MAKE) -C cn0363/cn0363_phase_data_sync clean
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$(MAKE) -C cn0363/cn0363_phase_data_sync clean
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@ -170,6 +171,7 @@ lib:
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$(MAKE) -C axi_spdif_rx
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$(MAKE) -C axi_spdif_rx
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$(MAKE) -C axi_spdif_tx
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$(MAKE) -C axi_spdif_tx
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$(MAKE) -C axi_sysid
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$(MAKE) -C axi_sysid
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$(MAKE) -C axi_tdd
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$(MAKE) -C axi_usb_fx3
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$(MAKE) -C axi_usb_fx3
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$(MAKE) -C cn0363/cn0363_dma_sequencer
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$(MAKE) -C cn0363/cn0363_dma_sequencer
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$(MAKE) -C cn0363/cn0363_phase_data_sync
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$(MAKE) -C cn0363/cn0363_phase_data_sync
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@ -0,0 +1,21 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_tdd
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GENERIC_DEPS += ../common/ad_addsub.v
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GENERIC_DEPS += ../common/ad_tdd_control.v
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GENERIC_DEPS += ../common/up_tdd_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += axi_tdd.v
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_tdd_constr.xdc
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XILINX_DEPS += axi_tdd_ip.tcl
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include ../scripts/library.mk
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@ -0,0 +1,324 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd (
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// clock
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input clk,
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input rst,
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// control signals from the tdd control
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output tdd_rx_vco_en,
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output tdd_tx_vco_en,
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output tdd_rx_rf_en,
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output tdd_tx_rf_en,
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// status signal
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output tdd_enabled,
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// sync signal
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input tdd_sync,
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output reg tdd_sync_cntr,
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// tx/rx data flow control
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output reg tdd_tx_valid,
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output reg tdd_rx_valid,
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// bus interface
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input s_axi_aresetn,
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input s_axi_aclk,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal signals
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wire up_rstn;
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wire up_clk;
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wire up_wreq;
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wire [13:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_rreq;
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wire [13:0] up_raddr;
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wire [31:0] up_rdata;
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wire up_rack;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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wire tdd_enable_s;
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wire tdd_secondary_s;
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wire [ 7:0] tdd_burst_count_s;
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wire tdd_rx_only_s;
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wire tdd_tx_only_s;
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wire tdd_gated_rx_dmapath_s;
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wire tdd_gated_tx_dmapath_s;
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_frame_length_s;
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wire tdd_terminal_type_s;
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wire tdd_sync_enable_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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wire [23:0] tdd_vco_tx_off_1_s;
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wire [23:0] tdd_rx_on_1_s;
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wire [23:0] tdd_rx_off_1_s;
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wire [23:0] tdd_rx_dp_on_1_s;
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wire [23:0] tdd_rx_dp_off_1_s;
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wire [23:0] tdd_tx_on_1_s;
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wire [23:0] tdd_tx_off_1_s;
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wire [23:0] tdd_tx_dp_on_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_vco_rx_on_2_s;
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wire [23:0] tdd_vco_rx_off_2_s;
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wire [23:0] tdd_vco_tx_on_2_s;
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wire [23:0] tdd_vco_tx_off_2_s;
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wire [23:0] tdd_rx_on_2_s;
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wire [23:0] tdd_rx_off_2_s;
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wire [23:0] tdd_rx_dp_on_2_s;
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wire [23:0] tdd_rx_dp_off_2_s;
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wire [23:0] tdd_tx_on_2_s;
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wire [23:0] tdd_tx_off_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire [ 7:0] tdd_status;
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wire [23:0] tdd_counter_status;
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wire tdd_rx_dp_en_s;
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wire tdd_tx_dp_en_s;
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reg tdd_vco_overlap;
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reg tdd_rf_overlap;
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assign tdd_enabled = tdd_enable_s;
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// syncronization control signal
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always @(posedge clk) begin
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if (tdd_enable_s == 1'b1) begin
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tdd_sync_cntr <= ~tdd_terminal_type_s;
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end else begin
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tdd_sync_cntr <= 1'b0;
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end
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end
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// tx/rx data flow control
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
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tdd_tx_valid <= tdd_tx_dp_en_s;
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end else begin
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tdd_tx_valid <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_rx_dmapath_s == 1)) begin
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tdd_rx_valid <= tdd_rx_dp_en_s;
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end else begin
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tdd_rx_valid <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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tdd_vco_overlap <= 1'b0;
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tdd_rf_overlap <= 1'b0;
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end else begin
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tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
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tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
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end
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end
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assign tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
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// instantiations
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up_tdd_cntrl #(
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.BASE_ADDRESS('h0))
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i_up_tdd_cntrl(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s),
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.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_terminal_type(tdd_terminal_type_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
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.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
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.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
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.tdd_tx_on_2(tdd_tx_on_2_s),
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.tdd_tx_off_2(tdd_tx_off_2_s),
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.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
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.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
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.tdd_status(tdd_status),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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ad_tdd_control #(
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.TX_DATA_PATH_DELAY(0),
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.CONTROL_PATH_DELAY(0))
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i_tdd_control(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_sync (tdd_sync),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
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.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
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.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
|
||||||
|
.tdd_tx_on_2(tdd_tx_on_2_s),
|
||||||
|
.tdd_tx_off_2(tdd_tx_off_2_s),
|
||||||
|
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
|
||||||
|
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
|
||||||
|
.tdd_rx_dp_en(tdd_rx_dp_en_s),
|
||||||
|
.tdd_tx_dp_en(tdd_tx_dp_en_s),
|
||||||
|
.tdd_rx_vco_en(tdd_rx_vco_en),
|
||||||
|
.tdd_tx_vco_en(tdd_tx_vco_en),
|
||||||
|
.tdd_rx_rf_en(tdd_rx_rf_en),
|
||||||
|
.tdd_tx_rf_en(tdd_tx_rf_en),
|
||||||
|
.tdd_counter_status(tdd_counter_status));
|
||||||
|
|
||||||
|
up_axi #(
|
||||||
|
.AXI_ADDRESS_WIDTH(16))
|
||||||
|
i_up_axi (
|
||||||
|
.up_rstn(s_axi_aresetn),
|
||||||
|
.up_clk(s_axi_aclk),
|
||||||
|
|
||||||
|
.up_axi_awvalid(s_axi_awvalid),
|
||||||
|
.up_axi_awaddr(s_axi_awaddr),
|
||||||
|
.up_axi_awready(s_axi_awready),
|
||||||
|
.up_axi_wvalid(s_axi_wvalid),
|
||||||
|
.up_axi_wdata(s_axi_wdata),
|
||||||
|
.up_axi_wstrb(s_axi_wstrb),
|
||||||
|
.up_axi_wready(s_axi_wready),
|
||||||
|
.up_axi_bvalid(s_axi_bvalid),
|
||||||
|
.up_axi_bresp(s_axi_bresp),
|
||||||
|
.up_axi_bready(s_axi_bready),
|
||||||
|
.up_axi_arvalid(s_axi_arvalid),
|
||||||
|
.up_axi_araddr(s_axi_araddr),
|
||||||
|
.up_axi_arready(s_axi_arready),
|
||||||
|
.up_axi_rvalid(s_axi_rvalid),
|
||||||
|
.up_axi_rresp(s_axi_rresp),
|
||||||
|
.up_axi_rdata(s_axi_rdata),
|
||||||
|
.up_axi_rready(s_axi_rready),
|
||||||
|
|
||||||
|
.up_wreq(up_wreq),
|
||||||
|
.up_waddr(up_waddr),
|
||||||
|
.up_wdata(up_wdata),
|
||||||
|
.up_wack(up_wack),
|
||||||
|
.up_rreq(up_rreq),
|
||||||
|
.up_raddr(up_raddr),
|
||||||
|
.up_rdata(up_rdata),
|
||||||
|
.up_rack(up_rack)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
# ip
|
||||||
|
|
||||||
|
source ../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||||
|
|
||||||
|
adi_ip_create axi_tdd
|
||||||
|
adi_ip_files axi_tdd [list \
|
||||||
|
"$ad_hdl_dir/library/common/ad_addsub.v" \
|
||||||
|
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||||
|
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||||
|
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||||
|
"axi_tdd_constr.xdc" \
|
||||||
|
"axi_tdd.v" ]
|
||||||
|
|
||||||
|
adi_ip_properties axi_tdd
|
||||||
|
set_property display_name "ADI AXI TDD Controller" [ipx::current_core]
|
||||||
|
set_property description "ADI AXI TDD Controller" [ipx::current_core]
|
||||||
|
|
||||||
|
adi_init_bd_tcl
|
||||||
|
|
||||||
|
proc add_reset {name polarity} {
|
||||||
|
set reset_intf [ipx::infer_bus_interface $name xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
|
||||||
|
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
|
||||||
|
set_property value $polarity $reset_polarity
|
||||||
|
}
|
||||||
|
|
||||||
|
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
|
||||||
|
add_reset rst ACTIVE_HIGH
|
||||||
|
add_reset s_axi_aresetn ACTIVE_LOW
|
||||||
|
|
||||||
|
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]
|
||||||
|
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
|
||||||
|
|
||||||
|
ipx::create_xgui_files [ipx::current_core]
|
||||||
|
|
||||||
|
ipx::save_core [ipx::current_core]
|
||||||
|
|
||||||
Loading…
Reference in New Issue