From 30ea87e60b4ba359b302eeb7f0543e45359ebae7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 9 Jul 2015 19:55:58 +0300 Subject: [PATCH] fmcadc4: Set explicit PCORE_ID for AD9680 --- projects/fmcadc4/common/fmcadc4_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index 2fc7efa30..3ad06ecd6 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -27,7 +27,9 @@ create_bd_port -dir I -from 255 -to 0 adc_ddata # adc peripherals set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0] +set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] +set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9680_core_1 set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd