axi_adc_trigger: Added trigger delay register, renamed fifo depth register
Adrian Costina
parent
491602d88b
commit
3148c85f73
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@ -53,7 +53,7 @@ module axi_adc_trigger(
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output data_valid_a_trig,
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output data_valid_b_trig,
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output [31:0] trigger_offset,
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output [31:0] fifo_depth,
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// axi interface
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@ -111,7 +111,7 @@ module axi_adc_trigger(
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wire [ 3:0] trigger_l_mix_b;
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wire [ 2:0] trigger_out_mix;
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wire [31:0] delay_trigger;
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wire [31:0] trigger_delay;
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wire [15:0] data_a_cmp;
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wire [15:0] data_b_cmp;
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@ -157,18 +157,20 @@ module axi_adc_trigger(
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reg trigger_out_mixed;
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reg [15:0] data_a_r;
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reg [15:0] data_b_r;
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reg [14:0] data_a_r;
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reg [14:0] data_b_r;
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reg data_valid_a_r;
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reg data_valid_b_r;
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reg [31:0] trigger_delay_counter;
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reg trigger_out_delayed;
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reg triggered;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign trigger_offset = delay_trigger;
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assign trigger_t = io_selection;
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assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0;
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@ -183,15 +185,35 @@ module axi_adc_trigger(
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assign limit_a_cmp = {!limit_a[15],limit_a[14:0]};
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assign limit_b_cmp = {!limit_b[15],limit_b[14:0]};
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assign data_a_trig = {trigger_out_mixed, data_a_r[14:0]};
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assign data_b_trig = {trigger_out_mixed, data_b_r[14:0]};;
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assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed, data_a_r} :{trigger_out_delayed, data_a_r} ;
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assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed, data_b_r} :{trigger_out_delayed, data_b_r};
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assign data_valid_a_trig = data_valid_a_r;
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assign data_valid_b_trig = data_valid_b_r;
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always @(posedge clk) begin
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data_a_r <= data_a;
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if (trigger_delay == 0) begin
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trigger_delay_counter <= 32'h0;
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end else begin
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if (data_valid_a_r == 1'b1) begin
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triggered <= trigger_out_mixed;
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trigger_out_delayed <= 1'b0;
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if (trigger_delay_counter == 0) begin
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trigger_delay_counter <= trigger_delay;
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trigger_out_delayed <= 1'b1;
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triggered <= 1'b0;
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end else begin
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if(triggered == 1'b1) begin
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trigger_delay_counter <= trigger_delay_counter - 1;
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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data_a_r <= data_a[14:0];
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data_valid_a_r <= data_valid_a;
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data_b_r <= data_b;
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data_b_r <= data_b[14:0];
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data_valid_b_r <= data_valid_b;
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end
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@ -362,7 +384,8 @@ module axi_adc_trigger(
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.trigger_l_mix_b(trigger_l_mix_b),
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.trigger_out_mix(trigger_out_mix),
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.delay_trigger(delay_trigger),
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.trigger_delay(trigger_delay),
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.fifo_depth(fifo_depth),
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// bus interface
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@ -60,7 +60,8 @@ module axi_adc_trigger_reg (
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output [ 3:0] trigger_l_mix_b,
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output [ 2:0] trigger_out_mix,
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output [31:0] delay_trigger,
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output [31:0] fifo_depth,
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output [31:0] trigger_delay,
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// bus interface
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@ -93,7 +94,8 @@ module axi_adc_trigger_reg (
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reg [31:0] up_hysteresis_b = 32'h0;
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reg [ 3:0] up_trigger_l_mix_b = 32'h0;
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reg [ 2:0] up_trigger_out_mix = 32'h0;
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reg [31:0] up_delay_trigger= 32'h0;
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reg [31:0] up_fifo_depth = 32'h0;
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reg [31:0] up_trigger_delay = 32'h0;
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reg up_triggered = 1'h0;
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assign low_level = config_trigger[1:0];
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@ -115,7 +117,8 @@ module axi_adc_trigger_reg (
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up_limit_b <= 'd0;
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up_function_b <= 'd0;
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up_hysteresis_b <= 'd0;
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up_delay_trigger <= 'd0;
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up_fifo_depth <= 'd0;
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up_trigger_delay <= 'd0;
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up_trigger_l_mix_a <= 'd0;
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up_trigger_l_mix_b <= 'd0;
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up_trigger_out_mix <= 'd0;
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@ -162,13 +165,16 @@ module axi_adc_trigger_reg (
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up_trigger_out_mix <= up_wdata[2:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
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up_delay_trigger <= up_wdata;
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up_fifo_depth <= up_wdata;
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end
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// if (triggered == 1'b1) begin
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// up_triggered <= 1'b1;
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// end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
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// up_triggered <= up_wdata[0];
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// end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
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up_trigger_delay <= up_wdata;
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end
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end
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end
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@ -196,8 +202,9 @@ module axi_adc_trigger_reg (
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5'hb: up_rdata <= up_hysteresis_b;
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5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b};
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5'hd: up_rdata <= {29'h0,up_trigger_out_mix};
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5'he: up_rdata <= up_delay_trigger;
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5'he: up_rdata <= up_fifo_depth;
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5'hf: up_rdata <= {31'h0,up_triggered};
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5'h10: up_rdata <= up_trigger_delay;
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default: up_rdata <= 0;
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endcase
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end else begin
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@ -206,7 +213,7 @@ module axi_adc_trigger_reg (
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end
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end
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up_xfer_cntrl #(.DATA_WIDTH(153)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(185)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_config_trigger, // 10
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@ -219,7 +226,8 @@ module axi_adc_trigger_reg (
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up_hysteresis_b, // 32
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up_trigger_l_mix_b, // 4
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up_trigger_out_mix, // 3
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up_delay_trigger}), // 32
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up_fifo_depth, // 32
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up_trigger_delay}), // 32
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.up_xfer_done (),
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.d_rst (1'b0),
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@ -234,7 +242,8 @@ module axi_adc_trigger_reg (
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hysteresis_b, // 32
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trigger_l_mix_b, // 4
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trigger_out_mix, // 3
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delay_trigger})); // 32
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fifo_depth, // 32
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trigger_delay})); // 32
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endmodule
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