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altera-9250/dma: make id width generic

main
Rejeesh Kutty 2014-04-24 14:53:09 -04:00
parent dfc2bba335
commit 314ec3d343
4 changed files with 111 additions and 87 deletions
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99
library/axi_ad9250/axi_ad9250_alt.v
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@ -102,72 +102,73 @@ module axi_ad9250_alt (
adc_mon_data); adc_mon_data);
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_DEVICE_TYPE = 0;
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
input rx_clk; input rx_clk;
input [63:0] rx_data; input [63:0] rx_data;
// dma interface // dma interface
output adc_clk; output adc_clk;
output adc_dwr; output adc_dwr;
output [63:0] adc_ddata; output [63:0] adc_ddata;
output adc_dsync; output adc_dsync;
input adc_dovf; input adc_dovf;
input adc_dunf; input adc_dunf;
// axi interface // axi interface
input s_axi_aclk; input s_axi_aclk;
input s_axi_aresetn; input s_axi_aresetn;
input s_axi_awvalid; input s_axi_awvalid;
input [13:0] s_axi_awaddr; input [13:0] s_axi_awaddr;
input [ 2:0] s_axi_awid; input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen; input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize; input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst; input [ 1:0] s_axi_awburst;
input [ 0:0] s_axi_awlock; input [ 0:0] s_axi_awlock;
input [ 3:0] s_axi_awcache; input [ 3:0] s_axi_awcache;
input [ 2:0] s_axi_awprot; input [ 2:0] s_axi_awprot;
output s_axi_awready; output s_axi_awready;
input s_axi_wvalid; input s_axi_wvalid;
input [31:0] s_axi_wdata; input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb; input [ 3:0] s_axi_wstrb;
input s_axi_wlast; input s_axi_wlast;
output s_axi_wready; output s_axi_wready;
output s_axi_bvalid; output s_axi_bvalid;
output [ 1:0] s_axi_bresp; output [ 1:0] s_axi_bresp;
output [ 2:0] s_axi_bid; output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready; input s_axi_bready;
input s_axi_arvalid; input s_axi_arvalid;
input [13:0] s_axi_araddr; input [13:0] s_axi_araddr;
input [ 2:0] s_axi_arid; input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen; input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize; input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst; input [ 1:0] s_axi_arburst;
input [ 0:0] s_axi_arlock; input [ 0:0] s_axi_arlock;
input [ 3:0] s_axi_arcache; input [ 3:0] s_axi_arcache;
input [ 2:0] s_axi_arprot; input [ 2:0] s_axi_arprot;
output s_axi_arready; output s_axi_arready;
output s_axi_rvalid; output s_axi_rvalid;
output [ 1:0] s_axi_rresp; output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata; output [31:0] s_axi_rdata;
output [ 2:0] s_axi_rid; output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast; output s_axi_rlast;
input s_axi_rready; input s_axi_rready;
// debug signals // debug signals
output adc_mon_valid; output adc_mon_valid;
output [119:0] adc_mon_data; output [119:0] adc_mon_data;
// defaults // defaults
assign s_axi_bid = 3'd0; assign s_axi_bid = 'd0;
assign s_axi_rid = 3'd0; assign s_axi_rid = 'd0;
assign s_axi_rlast = 1'd0; assign s_axi_rlast = 1'd0;
// ad9250 lite version // ad9250 lite version

15
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -44,6 +44,13 @@ set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
add_parameter PCORE_AXI_ID_WIDTH INTEGER 0
set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH
set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
# axi4 slave # axi4 slave
add_interface s_axi_clock clock end add_interface s_axi_clock clock end
@ -73,7 +80,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1 add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 3 add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_awlen awlen Input 8 add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3 add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2 add_interface_port s_axi s_axi_awburst awburst Input 2
@ -81,15 +88,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4 add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1 add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 3 add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arid arid Input 3 add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arlen arlen Input 8 add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3 add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2 add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1 add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4 add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3 add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 3 add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_rlast rlast Output 1 add_interface_port s_axi s_axi_rlast rlast Output 1

35
library/axi_dmac/axi_dmac_alt.v
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@ -184,9 +184,12 @@ module axi_dmac_alt (
fifo_rd_en, fifo_rd_en,
fifo_rd_valid, fifo_rd_valid,
fifo_rd_dout, fifo_rd_dout,
fifo_rd_underflow); fifo_rd_underflow,
irq);
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH_SRC = 64; parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64; parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 14; parameter C_DMA_LENGTH_WIDTH = 14;
@ -207,7 +210,7 @@ module axi_dmac_alt (
input s_axi_aresetn; input s_axi_aresetn;
input s_axi_awvalid; input s_axi_awvalid;
input [13:0] s_axi_awaddr; input [13:0] s_axi_awaddr;
input [ 2:0] s_axi_awid; input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen; input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize; input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst; input [ 1:0] s_axi_awburst;
@ -222,11 +225,11 @@ module axi_dmac_alt (
output s_axi_wready; output s_axi_wready;
output s_axi_bvalid; output s_axi_bvalid;
output [ 1:0] s_axi_bresp; output [ 1:0] s_axi_bresp;
output [ 2:0] s_axi_bid; output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready; input s_axi_bready;
input s_axi_arvalid; input s_axi_arvalid;
input [13:0] s_axi_araddr; input [13:0] s_axi_araddr;
input [ 2:0] s_axi_arid; input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen; input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize; input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst; input [ 1:0] s_axi_arburst;
@ -237,7 +240,7 @@ module axi_dmac_alt (
output s_axi_rvalid; output s_axi_rvalid;
output [ 1:0] s_axi_rresp; output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata; output [31:0] s_axi_rdata;
output [ 2:0] s_axi_rid; output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast; output s_axi_rlast;
input s_axi_rready; input s_axi_rready;
@ -247,7 +250,7 @@ module axi_dmac_alt (
input m_dest_axi_aresetn; input m_dest_axi_aresetn;
output m_dest_axi_awvalid; output m_dest_axi_awvalid;
output [31:0] m_dest_axi_awaddr; output [31:0] m_dest_axi_awaddr;
output [ 2:0] m_dest_axi_awid; output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_awid;
output [ 7:0] m_dest_axi_awlen; output [ 7:0] m_dest_axi_awlen;
output [ 2:0] m_dest_axi_awsize; output [ 2:0] m_dest_axi_awsize;
output [ 1:0] m_dest_axi_awburst; output [ 1:0] m_dest_axi_awburst;
@ -262,11 +265,11 @@ module axi_dmac_alt (
input m_dest_axi_wready; input m_dest_axi_wready;
input m_dest_axi_bvalid; input m_dest_axi_bvalid;
input [ 1:0] m_dest_axi_bresp; input [ 1:0] m_dest_axi_bresp;
input [ 2:0] m_dest_axi_bid; input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_bid;
output m_dest_axi_bready; output m_dest_axi_bready;
output m_dest_axi_arvalid; output m_dest_axi_arvalid;
output [31:0] m_dest_axi_araddr; output [31:0] m_dest_axi_araddr;
output [ 2:0] m_dest_axi_arid; output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_arid;
output [ 7:0] m_dest_axi_arlen; output [ 7:0] m_dest_axi_arlen;
output [ 2:0] m_dest_axi_arsize; output [ 2:0] m_dest_axi_arsize;
output [ 1:0] m_dest_axi_arburst; output [ 1:0] m_dest_axi_arburst;
@ -277,7 +280,7 @@ module axi_dmac_alt (
input m_dest_axi_rvalid; input m_dest_axi_rvalid;
input [ 1:0] m_dest_axi_rresp; input [ 1:0] m_dest_axi_rresp;
input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata; input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
input [ 2:0] m_dest_axi_rid; input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_rid;
input m_dest_axi_rlast; input m_dest_axi_rlast;
output m_dest_axi_rready; output m_dest_axi_rready;
@ -287,7 +290,7 @@ module axi_dmac_alt (
input m_src_axi_aresetn; input m_src_axi_aresetn;
output m_src_axi_awvalid; output m_src_axi_awvalid;
output [31:0] m_src_axi_awaddr; output [31:0] m_src_axi_awaddr;
output [ 2:0] m_src_axi_awid; output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_awid;
output [ 7:0] m_src_axi_awlen; output [ 7:0] m_src_axi_awlen;
output [ 2:0] m_src_axi_awsize; output [ 2:0] m_src_axi_awsize;
output [ 1:0] m_src_axi_awburst; output [ 1:0] m_src_axi_awburst;
@ -302,11 +305,11 @@ module axi_dmac_alt (
input m_src_axi_wready; input m_src_axi_wready;
input m_src_axi_bvalid; input m_src_axi_bvalid;
input [ 1:0] m_src_axi_bresp; input [ 1:0] m_src_axi_bresp;
input [ 2:0] m_src_axi_bid; input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_bid;
output m_src_axi_bready; output m_src_axi_bready;
output m_src_axi_arvalid; output m_src_axi_arvalid;
output [31:0] m_src_axi_araddr; output [31:0] m_src_axi_araddr;
output [ 2:0] m_src_axi_arid; output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_arid;
output [ 7:0] m_src_axi_arlen; output [ 7:0] m_src_axi_arlen;
output [ 2:0] m_src_axi_arsize; output [ 2:0] m_src_axi_arsize;
output [ 1:0] m_src_axi_arburst; output [ 1:0] m_src_axi_arburst;
@ -317,7 +320,7 @@ module axi_dmac_alt (
input m_src_axi_rvalid; input m_src_axi_rvalid;
input [ 1:0] m_src_axi_rresp; input [ 1:0] m_src_axi_rresp;
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata; input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
input [ 2:0] m_src_axi_rid; input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_rid;
input m_src_axi_rlast; input m_src_axi_rlast;
output m_src_axi_rready; output m_src_axi_rready;
@ -346,10 +349,12 @@ module axi_dmac_alt (
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout; output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout;
output fifo_rd_underflow; output fifo_rd_underflow;
output irq;
// defaults // defaults
assign s_axi_bid = 3'd0; assign s_axi_bid = 'd0;
assign s_axi_rid = 3'd0; assign s_axi_rid = 'd0;
assign s_axi_rlast = 1'd0; assign s_axi_rlast = 1'd0;
// instantiation // instantiation

49
library/axi_dmac/axi_dmac_hw.tcl
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@ -49,6 +49,13 @@ set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter PCORE_AXI_ID_WIDTH INTEGER 0
set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH
set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0 add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0
set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64 set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
@ -63,13 +70,6 @@ set_parameter_property C_DMA_DATA_WIDTH_DEST TYPE INTEGER
set_parameter_property C_DMA_DATA_WIDTH_DEST UNITS None set_parameter_property C_DMA_DATA_WIDTH_DEST UNITS None
set_parameter_property C_DMA_DATA_WIDTH_DEST HDL_PARAMETER true set_parameter_property C_DMA_DATA_WIDTH_DEST HDL_PARAMETER true
add_parameter C_ADDR_ALIGN_BITS INTEGER 0
set_parameter_property C_ADDR_ALIGN_BITS DEFAULT_VALUE 3
set_parameter_property C_ADDR_ALIGN_BITS DISPLAY_NAME C_ADDR_ALIGN_BITS
set_parameter_property C_ADDR_ALIGN_BITS TYPE INTEGER
set_parameter_property C_ADDR_ALIGN_BITS UNITS None
set_parameter_property C_ADDR_ALIGN_BITS HDL_PARAMETER true
add_parameter C_DMA_LENGTH_WIDTH INTEGER 0 add_parameter C_DMA_LENGTH_WIDTH INTEGER 0
set_parameter_property C_DMA_LENGTH_WIDTH DEFAULT_VALUE 14 set_parameter_property C_DMA_LENGTH_WIDTH DEFAULT_VALUE 14
set_parameter_property C_DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH set_parameter_property C_DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH
@ -176,7 +176,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1 add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 3 add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_awlen awlen Input 8 add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3 add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2 add_interface_port s_axi s_axi_awburst awburst Input 2
@ -184,17 +184,28 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4 add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1 add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 3 add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arid arid Input 3 add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arlen arlen Input 8 add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3 add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2 add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1 add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4 add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3 add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 3 add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_rlast rlast Output 1 add_interface_port s_axi s_axi_rlast rlast Output 1
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint ""
set_interface_property interrupt_sender associatedClock s_axi_clock
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1
# conditional interface # conditional interface
proc axi_dmac_elaborate {} { proc axi_dmac_elaborate {} {
@ -230,7 +241,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2 add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
add_interface_port m_dest_axi m_dest_axi_rready rready Output 1 add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
add_interface_port m_dest_axi m_dest_axi_awid awid Output 3 add_interface_port m_dest_axi m_dest_axi_awid awid Output PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8 add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3 add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2 add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
@ -238,15 +249,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4 add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3 add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1 add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
add_interface_port m_dest_axi m_dest_axi_bid bid Input 3 add_interface_port m_dest_axi m_dest_axi_bid bid Input PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_arid arid Output 3 add_interface_port m_dest_axi m_dest_axi_arid arid Output PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8 add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3 add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2 add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1 add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4 add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3 add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
add_interface_port m_dest_axi m_dest_axi_rid rid Input 3 add_interface_port m_dest_axi m_dest_axi_rid rid Input PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1 add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
} }
@ -279,7 +290,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2 add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rready rready Output 1 add_interface_port m_src_axi m_src_axi_rready rready Output 1
add_interface_port m_src_axi m_src_axi_awid awid Output 3 add_interface_port m_src_axi m_src_axi_awid awid Output PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8 add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3 add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
add_interface_port m_src_axi m_src_axi_awburst awburst Output 2 add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
@ -287,15 +298,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_awcache awcache Output 4 add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
add_interface_port m_src_axi m_src_axi_awprot awprot Output 3 add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
add_interface_port m_src_axi m_src_axi_wlast wlast Output 1 add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
add_interface_port m_src_axi m_src_axi_bid bid Input 3 add_interface_port m_src_axi m_src_axi_bid bid Input PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_arid arid Output 3 add_interface_port m_src_axi m_src_axi_arid arid Output PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_arlen arlen Output 8 add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
add_interface_port m_src_axi m_src_axi_arsize arsize Output 3 add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
add_interface_port m_src_axi m_src_axi_arburst arburst Output 2 add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
add_interface_port m_src_axi m_src_axi_arlock arlock Output 1 add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
add_interface_port m_src_axi m_src_axi_arcache arcache Output 4 add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
add_interface_port m_src_axi m_src_axi_arprot arprot Output 3 add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
add_interface_port m_src_axi m_src_axi_rid rid Input 3 add_interface_port m_src_axi m_src_axi_rid rid Input PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_rlast rlast Input 1 add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
} }