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adrv9371x: Set up the defualt clock output control 

The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.

The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
main
Istvan Csomortani 2018-03-22 13:17:24 +00:00 committed by István Csomortáni
parent 8b671fa7ae
commit 318dcbb5d9
1 changed files with 9 additions and 0 deletions
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9
projects/adrv9371x/common/adrv9371x_bd.tcl
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@ -18,6 +18,9 @@ ad_ip_instance axi_adxcvr axi_ad9371_tx_xcvr
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.LPM_OR_DFE_N 0
adi_axi_jesd204_tx_create axi_ad9371_tx_jesd 4
@ -50,6 +53,9 @@ ad_ip_instance axi_adxcvr axi_ad9371_rx_xcvr
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.LPM_OR_DFE_N 1
adi_axi_jesd204_rx_create axi_ad9371_rx_jesd 2
@ -83,6 +89,9 @@ ad_ip_instance axi_adxcvr axi_ad9371_rx_os_xcvr
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.LPM_OR_DFE_N 1
adi_axi_jesd204_rx_create axi_ad9371_rx_os_jesd 2