diff --git a/library/xilinx/common/ad_data_in.v b/library/xilinx/common/ad_data_in.v
index 1adcf9074..c0d17b191 100644
--- a/library/xilinx/common/ad_data_in.v
+++ b/library/xilinx/common/ad_data_in.v
@@ -41,6 +41,7 @@ module ad_data_in #(
 
   parameter   SINGLE_ENDED = 0,
   parameter   FPGA_TECHNOLOGY = 0,
+  parameter   IDDR_CLK_EDGE ="SAME_EDGE",
   parameter   IODELAY_ENABLE = 1,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
@@ -186,7 +187,7 @@ module ad_data_in #(
 
   generate
   if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
-  IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
+  IDDRE1 #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
     .R (1'b0),
     .C (rx_clk),
     .CB (~rx_clk),
@@ -198,7 +199,7 @@ module ad_data_in #(
 
   generate
   if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
+  IDDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
     .CE (1'b1),
     .R (1'b0),
     .S (1'b0),
diff --git a/library/xilinx/common/ad_data_out.v b/library/xilinx/common/ad_data_out.v
index f1640fc90..e19710013 100644
--- a/library/xilinx/common/ad_data_out.v
+++ b/library/xilinx/common/ad_data_out.v
@@ -39,6 +39,7 @@ module ad_data_out #(
 
   parameter   FPGA_TECHNOLOGY = 0,
   parameter   SINGLE_ENDED = 0,
+  parameter   IDDR_CLK_EDGE ="SAME_EDGE",
   parameter   IODELAY_ENABLE = 0,
   parameter   IODELAY_CTRL = 0,
   parameter   IODELAY_GROUP = "dev_if_delay_group",
@@ -112,7 +113,7 @@ module ad_data_out #(
 
   generate
   if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  ODDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_tx_data_oddr (
+  ODDR #(.DDR_CLK_EDGE ("IDDR_CLK_EDGE")) i_tx_data_oddr (
     .CE (1'b1),
     .R (1'b0),
     .S (1'b0),