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xilinx/common: Add CLKEDGE parameter to ad_data_* module

main
Adrian Costina 2021-11-05 14:34:59 +02:00
parent e4832cd027
commit 31c21cad7f
2 changed files with 5 additions and 3 deletions
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5
library/xilinx/common/ad_data_in.v
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@ -41,6 +41,7 @@ module ad_data_in #(
parameter SINGLE_ENDED = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter IDDR_CLK_EDGE ="SAME_EDGE",
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group",
@ -186,7 +187,7 @@ module ad_data_in #(
generate
if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
IDDRE1 #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
.R (1'b0),
.C (rx_clk),
.CB (~rx_clk),
@ -198,7 +199,7 @@ module ad_data_in #(
generate
if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
IDDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),

3
library/xilinx/common/ad_data_out.v
View File

@ -39,6 +39,7 @@ module ad_data_out #(
parameter FPGA_TECHNOLOGY = 0,
parameter SINGLE_ENDED = 0,
parameter IDDR_CLK_EDGE ="SAME_EDGE",
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group",
@ -112,7 +113,7 @@ module ad_data_out #(
generate
if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_tx_data_oddr (
ODDR #(.DDR_CLK_EDGE ("IDDR_CLK_EDGE")) i_tx_data_oddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),