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fmcomms6: Better cope with higher sample rates 

There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-12-04 13:27:58 +01:00
parent 46156b7ceb
commit 324c0528c2
1 changed files with 2 additions and 1 deletions
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3
projects/fmcomms6/common/fmcomms6_bd.tcl
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@ -65,6 +65,7 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_ad9652_dma
if {$sys_zynq == 0} {
@ -87,7 +88,7 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {170.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7