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fmcomms2_ALL: Add/fix ENABLE/TXNRX control 

Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
main
Istvan Csomortani 2015-07-03 12:55:37 +03:00
parent 5208ebedd5
commit 32ae7c771a
15 changed files with 1484 additions and 1365 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
projects/fmcomms2/ac701/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/ac701/system_top.v
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@ -97,8 +97,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -167,8 +168,9 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -190,12 +192,21 @@ module system_top (
wire spi_mosi; wire spi_mosi;
wire spi_miso; wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments // assignments
assign fan_pwm = 1'b1; assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1; assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0]; assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -278,7 +289,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin), .uart_sin (uart_sin),
.uart_sout (uart_sout)); .uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

3
projects/fmcomms2/common/fmcomms2_bd.tcl
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@ -18,6 +18,8 @@ create_bd_port -dir O -from 5 -to 0 tx_data_out_n
create_bd_port -dir O enable create_bd_port -dir O enable
create_bd_port -dir O txnrx create_bd_port -dir O txnrx
create_bd_port -dir O tdd_enable
# ad9361 core # ad9361 core
set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
@ -76,6 +78,7 @@ ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
ad_connect enable axi_ad9361/enable ad_connect enable axi_ad9361/enable
ad_connect txnrx axi_ad9361/txnrx ad_connect txnrx axi_ad9361/txnrx
ad_connect tdd_enable axi_ad9361/tdd_enable
ad_connect axi_ad9361_clk util_adc_pack/clk ad_connect axi_ad9361_clk util_adc_pack/clk
ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0 ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0
ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1 ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1

4
projects/fmcomms2/kc705/system_constr.xdc
View File

@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

29
projects/fmcomms2/kc705/system_top.v
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@ -109,8 +109,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -191,8 +192,8 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -214,6 +215,12 @@ module system_top (
wire spi_mosi; wire spi_mosi;
wire spi_miso; wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic // default logic
assign ddr3_1_p = 2'b11; assign ddr3_1_p = 2'b11;
@ -222,12 +229,15 @@ module system_top (
assign iic_rstn = 1'b1; assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0]; assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t (gpio_t[49:32]), .dio_t (gpio_t[48:32]),
.dio_i (gpio_o[49:32]), .dio_i (gpio_o[48:32]),
.dio_o (gpio_i[49:32]), .dio_o (gpio_i[48:32]),
.dio_p ({ gpio_txnrx, .dio_p ({ gpio_txnrx,
gpio_enable, gpio_enable,
gpio_resetb, gpio_resetb,
@ -314,7 +324,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin), .uart_sin (uart_sin),
.uart_sout (uart_sout)); .uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

4
projects/fmcomms2/mitx045/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

25
projects/fmcomms2/mitx045/system_top.v
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@ -96,8 +96,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -164,8 +165,8 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -183,6 +184,17 @@ module system_top (
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -282,7 +294,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n), .tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p)); .tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

25
projects/fmcomms2/rfsom/system_top.v
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@ -107,6 +107,7 @@ module system_top (
tx_frame_out_n, tx_frame_out_n,
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
enable, enable,
txnrx, txnrx,
@ -190,6 +191,7 @@ module system_top (
output tx_frame_out_n; output tx_frame_out_n;
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
output enable; output enable;
output txnrx; output txnrx;
@ -213,18 +215,28 @@ module system_top (
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments // assignments
assign hdmi_pd = 1'b0; assign hdmi_pd = 1'b0;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(19)) i_iobuf (
.dio_t ({gpio_t[50:49], gpio_t[46:32]}), .dio_t ({gpio_t[52:51], gpio_t[48:32]}),
.dio_i ({gpio_o[50:49], gpio_o[46:32]}), .dio_i ({gpio_o[52:51], gpio_o[48:32]}),
.dio_o ({gpio_i[50:49], gpio_i[46:32]}), .dio_o ({gpio_i[52:51], gpio_i[48:32]}),
.dio_p ({ gpio_rfpwr_enable, .dio_p ({ gpio_rfpwr_enable,
gpio_clksel, gpio_clksel,
gpio_txnrx,
gpio_enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -253,7 +265,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n), .ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n), .ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n), .ddr_we_n (ddr_we_n),
.enable (enable), .enable (enable_s),
.eth1_125mclk (), .eth1_125mclk (),
.eth1_25mclk (), .eth1_25mclk (),
.eth1_2m5clk (), .eth1_2m5clk (),
@ -336,7 +348,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx)); .txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

4
projects/fmcomms2/vc707/system_constr.xdc
View File

@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/vc707/system_top.v
View File

@ -104,8 +104,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -183,8 +184,9 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -206,12 +208,21 @@ module system_top (
wire spi_mosi; wire spi_mosi;
wire spi_miso; wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic // default logic
assign fan_pwm = 1'b1; assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1; assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0]; assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -301,7 +312,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin), .uart_sin (uart_sin),
.uart_sout (uart_sout)); .uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

4
projects/fmcomms2/zc702/system_constr.xdc
View File

@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

25
projects/fmcomms2/zc702/system_top.v
View File

@ -90,8 +90,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -152,8 +153,8 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -176,6 +177,17 @@ module system_top (
wire spi_udc_sclk; wire spi_udc_sclk;
wire spi_udc_data; wire spi_udc_data;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(29)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
@ -273,7 +285,10 @@ module system_top (
.spi1_csn_2_o(), .spi1_csn_2_o(),
.spi1_sdo_i (spi_udc_data), .spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data), .spi1_sdo_o (spi_udc_data),
.spi1_sdi_i (1'b0)); .spi1_sdi_i (1'b0),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

30
projects/fmcomms2/zc706/system_top.v
View File

@ -89,6 +89,7 @@ module system_top (
tx_frame_out_n, tx_frame_out_n,
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
enable, enable,
txnrx, txnrx,
@ -156,6 +157,7 @@ module system_top (
output tx_frame_out_n; output tx_frame_out_n;
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
output enable; output enable;
output txnrx; output txnrx;
@ -202,13 +204,26 @@ module system_top (
wire [31:0] dac_gpio_input; wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output; wire [31:0] dac_gpio_output;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t (gpio_t[46:32]), .dio_t (gpio_t[48:32]),
.dio_i (gpio_o[46:32]), .dio_i (gpio_o[48:32]),
.dio_o (gpio_i[46:32]), .dio_o (gpio_i[48:32]),
.dio_p ({ gpio_resetb, .dio_p ({ gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
gpio_ctl, gpio_ctl,
@ -236,7 +251,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n), .ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n), .ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n), .ddr_we_n (ddr_we_n),
.enable (enable), .enable (enable_s),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio), .fixed_io_mio (fixed_io_mio),
@ -296,7 +311,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx)); .txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule

4
projects/fmcomms2/zed/system_constr.xdc
View File

@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

26
projects/fmcomms2/zed/system_top.v
View File

@ -100,8 +100,9 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, txnrx,
gpio_enable, enable,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -177,8 +178,9 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output txnrx;
inout gpio_enable; output enable;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -207,6 +209,17 @@ module system_top (
wire [ 1:0] iic_mux_sda_o_s; wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s; wire iic_mux_sda_t_s;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations // instantiations
ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio ( ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio (
@ -319,7 +332,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n), .tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p)); .tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule endmodule