From 32b3cfd8b9fac6b68a5ce9b28cea1a53319ad21b Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 23 Oct 2015 13:27:00 +0300 Subject: [PATCH] axi_usb_fx3: Initial commit of the core with interface stub --- library/Makefile | 2 + library/axi_usb_fx3/Makefile | 46 ++ library/axi_usb_fx3/axi_usb_fx3.v | 462 ++++++++++++++++++ library/axi_usb_fx3/axi_usb_fx3_core.v | 643 +++++++++++++++++++++++++ library/axi_usb_fx3/axi_usb_fx3_if.v | 292 +++++++++++ library/axi_usb_fx3/axi_usb_fx3_ip.tcl | 36 ++ library/axi_usb_fx3/axi_usb_fx3_reg.v | 434 +++++++++++++++++ 7 files changed, 1915 insertions(+) create mode 100644 library/axi_usb_fx3/Makefile create mode 100644 library/axi_usb_fx3/axi_usb_fx3.v create mode 100644 library/axi_usb_fx3/axi_usb_fx3_core.v create mode 100644 library/axi_usb_fx3/axi_usb_fx3_if.v create mode 100644 library/axi_usb_fx3/axi_usb_fx3_ip.tcl create mode 100644 library/axi_usb_fx3/axi_usb_fx3_reg.v diff --git a/library/Makefile b/library/Makefile index 044f6b861..fdd46d564 100644 --- a/library/Makefile +++ b/library/Makefile @@ -39,6 +39,7 @@ clean: make -C axi_mc_speed clean make -C axi_spdif_rx clean make -C axi_spdif_tx clean + make -C axi_usb_fx3 clean make -C cn0363/cn0363_dma_sequencer clean make -C cn0363/cn0363_phase_data_sync clean make -C cordic_demod clean @@ -101,6 +102,7 @@ lib: -make -C axi_mc_speed -make -C axi_spdif_rx -make -C axi_spdif_tx + -make -C axi_usb_fx3 -make -C cn0363/cn0363_dma_sequencer -make -C cn0363/cn0363_phase_data_sync -make -C cordic_demod diff --git a/library/axi_usb_fx3/Makefile b/library/axi_usb_fx3/Makefile new file mode 100644 index 000000000..54123fcfc --- /dev/null +++ b/library/axi_usb_fx3/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := axi_usb_fx3_ip.tcl +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../common/up_axi.v +M_DEPS += axi_usb_fx3_core.v +M_DEPS += axi_usb_fx3_if.v +M_DEPS += axi_usb_fx3_reg.v +M_DEPS += axi_usb_fx3.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_usb_fx3.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_usb_fx3.xpr: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_VIVADO) axi_usb_fx3_ip.tcl >> axi_usb_fx3_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v new file mode 100644 index 000000000..f6e19cbdf --- /dev/null +++ b/library/axi_usb_fx3/axi_usb_fx3.v @@ -0,0 +1,462 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_usb_fx3 ( + + // gpif ii + + dma_rdy, + dma_wmk, + + fifo_rdy, + + pclk, //output clk 100 Mhz and 180 phase shift + + data, + addr, //output fifo address + + slcs_n, //output chip select + slrd_n, //output read select + sloe_n, //output output enable select + slwr_n, //output write select + pktend_n, //output pkt end + epswitch_n, //output EP Switch + + // irq + + irq, + + // DEBUG + debug_fx32dma, + debug_dma2fx3, + debug_status, + + // s2mm + + s_axis_tdata, + s_axis_tkeep, + s_axis_tlast, + s_axis_tvalid, + s_axis_tready, + + // mm2s + + m_axis_tready, + m_axis_tdata, + m_axis_tkeep, + m_axis_tlast, + m_axis_tvalid, + + // axi lite + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + // gpif ii + + input dma_rdy; + input dma_wmk; + + input [10:0] fifo_rdy; + + output pclk; + + output [31:0] data; + output [4:0] addr; + + output slcs_n; + output slrd_n; + output sloe_n; + output slwr_n; + output pktend_n; + output epswitch_n; + + // DEBUG + output [35:0] debug_fx32dma; + output [34:0] debug_dma2fx3; + output [14:0] debug_status; + + // irq + + output irq; + + // s2mm + + input [31:0] s_axis_tdata; + input [ 3:0] s_axis_tkeep; + input s_axis_tlast; + input s_axis_tvalid; + output s_axis_tready; + + // mm2s + + input m_axis_tready; + output [31:0] m_axis_tdata; + output [ 3:0] m_axis_tkeep; + output m_axis_tlast; + output m_axis_tvalid; + + // axi lite + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + + // internal clocks & resets + + wire up_rstn; + wire up_clk; + + // internal signals + + wire [13:0] up_raddr; + wire [31:0] up_rdata; + wire up_rack; + wire up_wack; + wire up_wreq; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_rreq_s; + + wire [ 7:0] fifo0_header_size; + wire [15:0] fifo0_buffer_size; + wire [ 7:0] fifo1_header_size; + wire [15:0] fifo1_buffer_size; + wire [ 7:0] fifo2_header_size; + wire [15:0] fifo2_buffer_size; + wire [ 7:0] fifo3_header_size; + wire [15:0] fifo3_buffer_size; + wire [ 7:0] fifo4_header_size; + wire [15:0] fifo4_buffer_size; + wire [ 7:0] fifo5_header_size; + wire [15:0] fifo5_buffer_size; + wire [ 7:0] fifo6_header_size; + wire [15:0] fifo6_buffer_size; + wire [ 7:0] fifo7_header_size; + wire [15:0] fifo7_buffer_size; + wire [ 7:0] fifo8_header_size; + wire [15:0] fifo8_buffer_size; + wire [ 7:0] fifo9_header_size; + wire [15:0] fifo9_buffer_size; + wire [ 7:0] fifoa_header_size; + wire [15:0] fifoa_buffer_size; + wire fifo0_direction; + wire fifo1_direction; + wire fifo2_direction; + wire fifo3_direction; + wire fifo4_direction; + wire fifo5_direction; + wire fifo6_direction; + wire fifo7_direction; + wire fifo8_direction; + wire fifo9_direction; + wire fifoa_direction; + + wire fx32dma_valid; + wire fx32dma_ready; + wire [31:0] fx32dma_data; + wire fx32dma_sop; + wire fx32dma_eop; + + wire dma2fx3_ready; + wire dma2fx3_valid; + wire [31:0] dma2fx3_data; + wire dma2fx3_eop; + + wire [ 2:0] test_mode_tpm; + wire [ 2:0] test_mode_tpg; + wire monitor_error; + wire eot_fx32dma; + wire eot_dma2fx3; + + wire error; + wire [ 4:0] fifo_num; + wire [10:0] fifo_ready; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign pclk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // DEBUG + + assign debug_dma2fx3 = {dma2fx3_ready, dma2fx3_valid, dma2fx3_data, dma2fx3_eop}; + assign debug_fx32dma = {fx32dma_eop,fx32dma_ready, fx32dma_valid, fx32dma_data, fx32dma_sop}; + assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num}; + + // packetizer, TPM/TPG and DMA interface + + axi_usb_fx3_core ep_packetizer( + .clk(pclk), + .reset(!up_rstn), + + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tlast(s_axis_tlast), + .s_axis_tready(s_axis_tready), + .s_axis_tvalid(s_axis_tvalid), + + .m_axis_tdata(m_axis_tdata), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_tlast(m_axis_tlast), + .m_axis_tready(m_axis_tready), + .m_axis_tvalid(m_axis_tvalid), + + .fifo0_header_size(fifo0_header_size), + .fifo0_buffer_size(fifo0_buffer_size), + .fifo1_header_size(fifo1_header_size), + .fifo1_buffer_size(fifo1_buffer_size), + .fifo2_header_size(fifo2_header_size), + .fifo2_buffer_size(fifo2_buffer_size), + .fifo3_header_size(fifo3_header_size), + .fifo3_buffer_size(fifo3_buffer_size), + .fifo4_header_size(fifo4_header_size), + .fifo4_buffer_size(fifo4_buffer_size), + .fifo5_header_size(fifo5_header_size), + .fifo5_buffer_size(fifo5_buffer_size), + .fifo6_header_size(fifo6_header_size), + .fifo6_buffer_size(fifo6_buffer_size), + .fifo7_header_size(fifo7_header_size), + .fifo7_buffer_size(fifo7_buffer_size), + .fifo8_header_size(fifo8_header_size), + .fifo8_buffer_size(fifo8_buffer_size), + .fifo9_header_size(fifo9_header_size), + .fifo9_buffer_size(fifo9_buffer_size), + .fifoa_header_size(fifoa_header_size), + .fifoa_buffer_size(fifoa_buffer_size), + + .fx32dma_valid(fx32dma_valid), + .fx32dma_ready(fx32dma_ready), + .fx32dma_data(fx32dma_data), + .fx32dma_sop(fx32dma_sop), + .fx32dma_eop(fx32dma_eop), + + .dma2fx3_ready(dma2fx3_ready), + .dma2fx3_valid(dma2fx3_valid), + .dma2fx3_data(dma2fx3_data), + .dma2fx3_eop(dma2fx3_eop), + + .error(error), + .eot_fx32dma(eot_fx32dma), + .eot_dma2fx3(eot_dma2fx3), + + .test_mode_tpm(test_mode_tpm), + .test_mode_tpg(test_mode_tpg), + .monitor_error(monitor_error), + + .fifo_num(fifo_num)); + + // register map + + axi_usb_fx3_reg fx3_registers( + + .fifo_rdy(fifo_ready), + + .eot_fx32dma(eot_fx32dma), + .eot_dma2fx3(eot_dma2fx3), + .trig(trig), + .fifo_num(fifo_num), + + .error(error), + + .test_mode_tpm(test_mode_tpm), + .test_mode_tpg(test_mode_tpg), + .monitor_error(monitor_error), + + .irq(irq), + + .fifo0_direction(fifo0_direction), + .fifo0_header_size(fifo0_header_size), + .fifo0_buffer_size(fifo0_buffer_size), + + .fifo1_direction(fifo1_direction), + .fifo1_header_size(fifo1_header_size), + .fifo1_buffer_size(fifo1_buffer_size), + + .fifo2_direction(fifo2_direction), + .fifo2_header_size(fifo2_header_size), + .fifo2_buffer_size(fifo2_buffer_size), + + .fifo3_direction(fifo3_direction), + .fifo3_header_size(fifo3_header_size), + .fifo3_buffer_size(fifo3_buffer_size), + + .fifo4_direction(fifo4_direction), + .fifo4_header_size(fifo4_header_size), + .fifo4_buffer_size(fifo4_buffer_size), + + .fifo5_direction(fifo5_direction), + .fifo5_header_size(fifo5_header_size), + .fifo5_buffer_size(fifo5_buffer_size), + + .fifo6_direction(fifo6_direction), + .fifo6_header_size(fifo6_header_size), + .fifo6_buffer_size(fifo6_buffer_size), + + .fifo7_direction(fifo7_direction), + .fifo7_header_size(fifo7_header_size), + .fifo7_buffer_size(fifo7_buffer_size), + + .fifo8_direction(fifo8_direction), + .fifo8_header_size(fifo8_header_size), + .fifo8_buffer_size(fifo8_buffer_size), + + .fifo9_direction(fifo9_direction), + .fifo9_header_size(fifo9_header_size), + .fifo9_buffer_size(fifo9_buffer_size), + + .fifoa_direction(fifoa_direction), + .fifoa_header_size(fifoa_header_size), + .fifoa_buffer_size(fifoa_buffer_size), + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + // GPIF II interface + + axi_usb_fx3_if fx3_if( + + .dma_rdy(dma_rdy), + .dma_wmk(dma_wmk), + .fifo_rdy(fifo_rdy), + .pclk(pclk), //output clk 100 Mhz and 180 phase shift + .data(data), + .addr(addr), //output fifo address + .slcs_n(slcs_n), //output chip select + .slrd_n(slrd_n), //output read select + .sloe_n(sloe_n), //output output enable select + .slwr_n(slwr_n), //output write select + .pktend_n(pktend_n), //output pkt end + .epswitch_n(epswitch_n), //output pkt end + .fifo_num(fifo_num), + .trig(trig), + .test_mode_tpm(test_mode_tpm), + .fifo_ready(fifo_ready), + + .fx32dma_valid(fx32dma_valid), + .fx32dma_ready(fx32dma_ready), + .fx32dma_data(fx32dma_data), + .fx32dma_sop(fx32dma_sop), + .fx32dma_eop(fx32dma_eop), + + .dma2fx3_ready(dma2fx3_ready), + .dma2fx3_valid(dma2fx3_valid), + .dma2fx3_data(dma2fx3_data), + .dma2fx3_eop(dma2fx3_eop)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v new file mode 100644 index 000000000..e0ed6114e --- /dev/null +++ b/library/axi_usb_fx3/axi_usb_fx3_core.v @@ -0,0 +1,643 @@ + +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_usb_fx3_core ( + + clk, + reset, + + // s2mm + + s_axis_tdata, + s_axis_tkeep, + s_axis_tlast, + s_axis_tready, + s_axis_tvalid, + + // mm2s + + m_axis_tdata, + m_axis_tkeep, + m_axis_tlast, + m_axis_tready, + m_axis_tvalid, + + // configuration + + fifo0_header_size, + fifo0_buffer_size, + + fifo1_header_size, + fifo1_buffer_size, + + fifo2_header_size, + fifo2_buffer_size, + + fifo3_header_size, + fifo3_buffer_size, + + fifo4_header_size, + fifo4_buffer_size, + + fifo5_header_size, + fifo5_buffer_size, + + fifo6_header_size, + fifo6_buffer_size, + + fifo7_header_size, + fifo7_buffer_size, + + fifo8_header_size, + fifo8_buffer_size, + + fifo9_header_size, + fifo9_buffer_size, + + fifoa_header_size, + fifoa_buffer_size, + + fifob_header_size, + fifob_buffer_size, + + fifoc_header_size, + fifoc_buffer_size, + + fifod_header_size, + fifod_buffer_size, + + fifoe_header_size, + fifoe_buffer_size, + + fifof_header_size, + fifof_buffer_size, + + // fx3 interface + // IN -> TO HOST / FX3 + // OUT -> FROM HOST / FX3 + + fx32dma_valid, + fx32dma_ready, + fx32dma_data, + fx32dma_sop, + fx32dma_eop, + + dma2fx3_ready, + dma2fx3_valid, + dma2fx3_data, + dma2fx3_eop, + + error, + eot_fx32dma, + eot_dma2fx3, + + test_mode_tpm, + test_mode_tpg, + monitor_error, + + fifo_num); + + input clk; + input reset; + + // s2mm + + input m_axis_tready; + output [31:0] m_axis_tdata; + output [ 3:0] m_axis_tkeep; + output m_axis_tlast; + output m_axis_tvalid; + + // mm2s + + input [31:0] s_axis_tdata; + input [ 3:0] s_axis_tkeep; + input s_axis_tlast; + input s_axis_tvalid; + output s_axis_tready; + + // configuration + + input [ 7:0] fifo0_header_size; + input [15:0] fifo0_buffer_size; + + input [ 7:0] fifo1_header_size; + input [15:0] fifo1_buffer_size; + + input [ 7:0] fifo2_header_size; + input [15:0] fifo2_buffer_size; + + input [ 7:0] fifo3_header_size; + input [15:0] fifo3_buffer_size; + + input [ 7:0] fifo4_header_size; + input [15:0] fifo4_buffer_size; + + input [ 7:0] fifo5_header_size; + input [15:0] fifo5_buffer_size; + + input [ 7:0] fifo6_header_size; + input [15:0] fifo6_buffer_size; + + input [ 7:0] fifo7_header_size; + input [15:0] fifo7_buffer_size; + + input [ 7:0] fifo8_header_size; + input [15:0] fifo8_buffer_size; + + input [ 7:0] fifo9_header_size; + input [15:0] fifo9_buffer_size; + + input [ 7:0] fifoa_header_size; + input [15:0] fifoa_buffer_size; + + input [ 7:0] fifob_header_size; + input [15:0] fifob_buffer_size; + + input [ 7:0] fifoc_header_size; + input [15:0] fifoc_buffer_size; + + input [ 7:0] fifod_header_size; + input [15:0] fifod_buffer_size; + + input [ 7:0] fifoe_header_size; + input [15:0] fifoe_buffer_size; + + input [ 7:0] fifof_header_size; + input [15:0] fifof_buffer_size; + + // FX3 interface + // IN -> ZYNQ TO HOST / FX3 + // OUT -> ZYNQ FROM HOST / FX3 + + input fx32dma_valid; + output fx32dma_ready; + input [31:0] fx32dma_data; + input fx32dma_sop; + input fx32dma_eop; + + input dma2fx3_ready; + output dma2fx3_valid; + output [31:0] dma2fx3_data; + output dma2fx3_eop; + + output error; + output eot_fx32dma; + output eot_dma2fx3; + + input [ 2:0] test_mode_tpm; + input [ 2:0] test_mode_tpg; + output monitor_error; + + input [ 4:0] fifo_num; + + // internal parameters + + localparam IDLE = 3'b001; + localparam READ_HEADER = 3'b010; + localparam ADD_FOOTER = 3'b010; + localparam READ_DATA = 3'b100; + + // internal signals + + wire test_mode_active_tpm; + wire test_mode_active_tpg; + + // internal registers + + reg [31:0] data_size_transaction = 32'h0; + reg [15:0] buffer_size_current = 16'h0; + reg [ 7:0] header_size_current = 8'h0; + + reg [31:0] m_axis_tdata = 32'h0; + reg [ 3:0] m_axis_tkeep = 4'h0; + reg m_axis_tlast = 1'b0; + reg m_axis_tvalid = 1'b0; + + reg eot_fx32dma = 1'b0; + reg eot_dma2fx3 = 1'b0; + + reg error_fx32dma = 1'b0; + reg error_dma2fx3 = 1'b0; + + reg [ 2:0] state_fx32dma = 3'h0; + reg [ 2:0] next_state_fx32dma = 3'h0; + + reg [ 2:0] state_dma2fx3 = 3'h0; + reg [ 2:0] next_state_dma2fx3 = 3'h0; + + reg [ 7:0] header_pointer = 8'h0; + reg header_read = 1'b0; + + reg [31:0] dma2fx3_counter = 1'b0; + reg [31:0] footer_pointer = 1'b0; + + reg s_axis_tready = 1'b0; + reg dma2fx3_valid = 1'b0; + reg [31:0] dma2fx3_data = 32'h0; + reg dma2fx3_eop = 1'b0; + + reg [31:0] expected_data = 32'h0; + reg monitor_error = 1'b0; + reg first_transfer = 1'b0; + + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + assign error = error_fx32dma | error_dma2fx3; + + assign test_mode_active_tpm = |test_mode_tpm; + assign test_mode_active_tpg = |test_mode_tpg; + + // fx32dma + + assign fx32dma_ready = m_axis_tready; + + // state machine + + always @(posedge clk) begin + if (reset == 1'b1 || error_fx32dma == 1'b1) begin + state_fx32dma <= IDLE; + end else begin + state_fx32dma <= next_state_fx32dma; + end + end + + always @(*) begin + case(state_fx32dma) + IDLE: + if(fx32dma_sop == 1'b1) begin + next_state_fx32dma = READ_HEADER; + end else begin + next_state_fx32dma = state_fx32dma; + end + READ_HEADER: + if(header_read == 1'b1) begin + next_state_fx32dma = READ_DATA; + end else begin + next_state_fx32dma = state_fx32dma; + end + READ_DATA: + if(data_size_transaction <= 4) begin + next_state_fx32dma = IDLE; + end else begin + next_state_fx32dma = state_fx32dma; + end + default: next_state_fx32dma = IDLE; + endcase + end + + always @(posedge clk) begin + case(state_fx32dma) + IDLE: begin + m_axis_tvalid <= 1'b0; + m_axis_tkeep <= 4'h0; + m_axis_tlast <= 1'b0; + error_fx32dma <= 1'b0; + eot_fx32dma <= 1'b0; + header_read <= 1'b0; + header_pointer <= 8'h4; + first_transfer <= 1'b1; + monitor_error <= 1'b0; + if (fx32dma_sop == 1'b1) begin + if(fx32dma_valid == 1'b1) begin + if(fx32dma_data != 32'hf00ff00f) begin + error_fx32dma <= 1'b1; + end else begin + error_fx32dma <= 1'b0; + end + end + end + case (test_mode_tpm) + 4'h1: expected_data <= 32'haaaaaaaa; + default: expected_data <= 32'hffffffff; + endcase + end + READ_HEADER: begin + m_axis_tvalid <= 1'b0; + m_axis_tkeep <= 4'h0; + m_axis_tlast <= 1'b0; + error_fx32dma <= 1'b0; + eot_fx32dma <= 1'b0; + first_transfer <= 1'b1; + monitor_error <= 1'b0; + if( fx32dma_valid == 1'b1) begin + if(header_pointer < header_size_current - 8) begin + header_pointer <= header_pointer + 4; + end else begin + header_read <= 1'b1; + end + if (header_pointer == 4) begin + data_size_transaction <= fx32dma_data; + if (fx32dma_data > buffer_size_current) begin + error_fx32dma <= 1'b1; + end + end + end + end + READ_DATA: begin + m_axis_tvalid <= fx32dma_valid; + m_axis_tdata <= fx32dma_data; + if (fx32dma_valid == 1'b1) begin + first_transfer <= 1'b0; + if (data_size_transaction > 4) begin + m_axis_tkeep <= 4'hf; + m_axis_tlast <= 1'b0; + data_size_transaction <= data_size_transaction - 4; + end else begin + m_axis_tlast <= 1'b1; + eot_fx32dma <= 1'b1; + case (data_size_transaction) + 1: m_axis_tkeep <= 4'h1; + 2: m_axis_tkeep <= 4'h3; + 3: m_axis_tkeep <= 4'h7; + default: m_axis_tkeep <= 4'hf; + endcase + end + end + // monitor + if (test_mode_active_tpm == 1'b1) begin + if (first_transfer == 1) begin + expected_data <= fx32dma_data; + end else begin + case (test_mode_tpm) + 4'h1: expected_data <= ~expected_data; + 4'h2: expected_data <= ~expected_data; + 4'h3: expected_data <= pn9(expected_data); + 4'h4: expected_data <= pn23(expected_data); + 4'h7: expected_data <= expected_data + 1; + default: expected_data <= 0; + endcase + if (expected_data != m_axis_tdata) begin + monitor_error <= 1'b1; + end else begin + monitor_error <= 1'b0; + end + end + end + end + endcase + end + + always @(*) begin + case (fifo_num) + 5'h0: buffer_size_current = fifo0_buffer_size; + 5'h1: buffer_size_current = fifo1_buffer_size; + 5'h2: buffer_size_current = fifo2_buffer_size; + 5'h3: buffer_size_current = fifo3_buffer_size; + 5'h4: buffer_size_current = fifo4_buffer_size; + 5'h5: buffer_size_current = fifo5_buffer_size; + 5'h6: buffer_size_current = fifo6_buffer_size; + 5'h7: buffer_size_current = fifo7_buffer_size; + 5'h8: buffer_size_current = fifo8_buffer_size; + 5'h9: buffer_size_current = fifo9_buffer_size; + 5'ha: buffer_size_current = fifoa_buffer_size; + 5'hb: buffer_size_current = fifob_buffer_size; + 5'hc: buffer_size_current = fifoc_buffer_size; + 5'hd: buffer_size_current = fifod_buffer_size; + 5'he: buffer_size_current = fifoe_buffer_size; + 5'hf: buffer_size_current = fifof_buffer_size; + default: buffer_size_current = fifo0_buffer_size; + endcase + case (fifo_num) + 5'h0: header_size_current = fifo0_header_size; + 5'h1: header_size_current = fifo1_header_size; + 5'h2: header_size_current = fifo2_header_size; + 5'h3: header_size_current = fifo3_header_size; + 5'h4: header_size_current = fifo4_header_size; + 5'h5: header_size_current = fifo5_header_size; + 5'h6: header_size_current = fifo6_header_size; + 5'h7: header_size_current = fifo7_header_size; + 5'h8: header_size_current = fifo8_header_size; + 5'h9: header_size_current = fifo9_header_size; + 5'ha: header_size_current = fifoa_header_size; + 5'hb: header_size_current = fifob_header_size; + 5'hc: header_size_current = fifoc_header_size; + 5'hd: header_size_current = fifod_header_size; + 5'he: header_size_current = fifoe_header_size; + 5'hf: header_size_current = fifof_header_size; + default: header_size_current = fifo0_header_size; + endcase + end + + // dma2fx3 + + always @(posedge clk) begin + if (reset == 1'b1 || error_dma2fx3 == 1'b1) begin + state_dma2fx3 <= IDLE; + end else begin + state_dma2fx3 <= next_state_dma2fx3; + end + end + + always @(*) begin + case(state_dma2fx3) + IDLE: + if(dma2fx3_ready == 1'b1) begin + next_state_dma2fx3 = READ_DATA; + end else begin + next_state_dma2fx3 = state_dma2fx3; + end + READ_DATA: + if(s_axis_tlast == 1'b1 || dma2fx3_counter >= buffer_size_current - 4) begin + next_state_dma2fx3 = ADD_FOOTER; + end else begin + next_state_dma2fx3 = state_dma2fx3; + end + ADD_FOOTER: + if(dma2fx3_eop == 1'b1) begin + next_state_dma2fx3 = IDLE; + end else begin + next_state_dma2fx3 = state_dma2fx3; + end + default: next_state_dma2fx3 = IDLE; + endcase + end + + always @(posedge clk) begin + case(state_dma2fx3) + IDLE: begin + dma2fx3_eop <= 1'b0; + eot_dma2fx3 <= 1'b0; + s_axis_tready <= 1'b0; + footer_pointer <= 0; + dma2fx3_counter <= 0; + dma2fx3_valid <= 1'b0; + case (test_mode_tpg) + 4'h1: dma2fx3_data <= 32'haaaaaaaa; + default: dma2fx3_data <= 32'hffffffff; + endcase + end + READ_DATA: begin + dma2fx3_eop <= 1'b0; + eot_dma2fx3 <= 1'b0; + footer_pointer <= 0; + if (test_mode_active_tpg == 1'b1) begin + s_axis_tready <= 1'b0; + dma2fx3_valid <= 1'b1; + if (dma2fx3_ready == 1'b1) begin + dma2fx3_counter <= dma2fx3_counter + 4; + case (test_mode_tpg) + 4'h1: dma2fx3_data <= ~dma2fx3_data; + 4'h2: dma2fx3_data <= ~dma2fx3_data; + 4'h3: dma2fx3_data <= pn9(dma2fx3_data); + 4'h4: dma2fx3_data <= pn23(dma2fx3_data); + 4'h7: dma2fx3_data <= dma2fx3_data + 1; + default: dma2fx3_data <= 0; + endcase + end + end else begin + dma2fx3_data <= s_axis_tdata; + if (s_axis_tlast == 1'b0) begin + s_axis_tready <= dma2fx3_ready; + end else begin + s_axis_tready <= 1'b0; + end + dma2fx3_valid <= s_axis_tvalid & s_axis_tready; + if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin + case (s_axis_tkeep) + 1: dma2fx3_counter <= dma2fx3_counter + 1; + 3: dma2fx3_counter <= dma2fx3_counter + 2; + 7: dma2fx3_counter <= dma2fx3_counter + 3; + default: dma2fx3_counter <= dma2fx3_counter + 4; + endcase + end + end + end + ADD_FOOTER: begin + dma2fx3_valid <= ~eot_dma2fx3; + dma2fx3_eop <= 1'b0; + eot_dma2fx3 <= 1'b0; + s_axis_tready <= 1'b0; + footer_pointer <= footer_pointer + 4; + case(footer_pointer) + 32'h0: dma2fx3_data <= 32'hf00ff00f; + 32'h4: dma2fx3_data <= dma2fx3_counter; + 32'h8: dma2fx3_data <= 32'h0; + default: dma2fx3_data <= 32'h0; + endcase + if (footer_pointer == header_size_current - 4) begin + dma2fx3_eop <= 1'b1; + eot_dma2fx3 <= 1'b1; + end + end + endcase + end + +endmodule diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v new file mode 100644 index 000000000..7e1a1f6aa --- /dev/null +++ b/library/axi_usb_fx3/axi_usb_fx3_if.v @@ -0,0 +1,292 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_usb_fx3_if ( + + dma_rdy, + dma_wmk, + + fifo_rdy, + + pclk, //output clk 100 Mhz and 180 phase shift + + data, + addr, //output fifo address + + slcs_n, //output chip select + slrd_n, //output read select + sloe_n, //output output enable select + slwr_n, //output write select + pktend_n, //output pkt end + epswitch_n, //output pkt end + + fifo_num, + trig, + fifo_ready, + + test_mode_tpm, + + fx32dma_valid, + fx32dma_ready, + fx32dma_data, + fx32dma_sop, + fx32dma_eop, + + dma2fx3_ready, + dma2fx3_valid, + dma2fx3_data, + dma2fx3_eop); + + input dma_rdy; + input dma_wmk; + + input [10:0] fifo_rdy; + + input pclk; + + output [31:0] data; + output [4:0] addr; + + output slcs_n; + output slrd_n; + output sloe_n; + output slwr_n; + output pktend_n; + output epswitch_n; + + output [10:0] fifo_ready; + + input [ 2:0] test_mode_tpm; + + input [4:0] fifo_num; + input trig; + + output fx32dma_valid; + input fx32dma_ready; + output [31:0] fx32dma_data; + output fx32dma_sop; + output fx32dma_eop; + + input dma2fx3_valid; + output dma2fx3_ready; + input [31:0] dma2fx3_data; + input dma2fx3_eop; + + // internal wires + + wire fx32dma_sop; + + // internal registers + + wire fx32dma_valid; + + reg [10:0] fifo_ready; + + reg internal_trig = 0; + reg trig_d = 0; + reg [31:0] internal_counter = 0; + reg [ 2:0] packet_number = 0; + reg [31:0] data_size = 0; + reg [31:0] fx32dma_data = 0; + reg [31:0] generated_data = 0; + reg fx32dma_eop; + + reg transaction_in_progress = 0; + + assign fx32dma_sop = internal_trig ; + assign fx32dma_valid = transaction_in_progress; + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + always @(posedge pclk) begin + trig_d <= trig; + fx32dma_eop <= 1'b0; + internal_trig <= trig & ~trig_d; + if (transaction_in_progress == 1'b0) begin + transaction_in_progress <= trig & ~trig_d; + end else begin + if (internal_counter >= data_size + 12) begin + transaction_in_progress = 1'b0; + fx32dma_eop <= 1'b1; + end + end + end + + always @(posedge pclk) begin + if (internal_trig == 1'b1 )begin + internal_counter <= 4; + packet_number <= packet_number + 1; + end else if (transaction_in_progress == 1'b1) begin + internal_counter <= internal_counter + 4; + end else begin + internal_counter <= 0; + end + end + + always @(packet_number) begin + case (packet_number) + 0: data_size = 1; + 1: data_size = 2; + 2: data_size = 3; + 3: data_size = 4; + 4: data_size = 512; + 5: data_size = 1024; + 6: data_size = 32767; + 7: data_size = 32768; + default: data_size = 16; + endcase + end + + always@(internal_counter, data_size, internal_counter, generated_data) begin + case (internal_counter) + 5'h0: fx32dma_data <= 32'hf00ff00f; + 5'h4: fx32dma_data <= data_size; + 5'h8: fx32dma_data <= 0; + 5'hc: fx32dma_data <= 32'hffffffff; + default: fx32dma_data <= generated_data; + endcase + end + + always @(posedge pclk) begin + if (fx32dma_sop == 1'b1) begin + if (test_mode_tpm == 3'h1) begin + generated_data <= 32'haaaaaaaa; + end else begin + generated_data <= 32'hffffffff; + end + end else begin + case(test_mode_tpm) + 4'h0: generated_data <= generated_data + 32'h10; + 4'h1: generated_data <= ~generated_data; + 4'h2: generated_data <= ~generated_data; + 4'h3: generated_data <= pn9(generated_data); + 4'h4: generated_data <= pn23(generated_data); + 4'h7: generated_data <= generated_data + 1; + default: generated_data <= generated_data + 32'h10; + endcase + end + end + // dma2fx3 + + assign dma2fx3_ready = 1'b1; + assign data = dma2fx3_data; + assign pktend_n = ~dma2fx3_eop; + assign slwr_n = ~dma2fx3_valid; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl new file mode 100644 index 000000000..fc62ff2c6 --- /dev/null +++ b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl @@ -0,0 +1,36 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_usb_fx3 +adi_ip_files axi_usb_fx3 [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_usb_fx3_core.v" \ + "axi_usb_fx3_if.v" \ + "axi_usb_fx3_reg.v" \ + "axi_usb_fx3.v"] + +adi_ip_properties axi_usb_fx3 + +ipx::remove_bus_interface rst [ipx::current_core] +ipx::remove_bus_interface clk [ipx::current_core] +ipx::remove_bus_interface l_clk [ipx::current_core] +ipx::remove_bus_interface delay_clk [ipx::current_core] + +adi_add_bus_clock "s_axi_aclk" "s_axis" +adi_add_bus_clock "s_axi_aclk" "m_axis" + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +#adi_ip_constraints axi_usb_fx3 [list \ +# "axi_usb_fx3_constr.xdc" ] + +#set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +#set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] diff --git a/library/axi_usb_fx3/axi_usb_fx3_reg.v b/library/axi_usb_fx3/axi_usb_fx3_reg.v new file mode 100644 index 000000000..3d9c6e750 --- /dev/null +++ b/library/axi_usb_fx3/axi_usb_fx3_reg.v @@ -0,0 +1,434 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_usb_fx3_reg ( + + // gpif ii + + fifo_rdy, + + eot_fx32dma, + eot_dma2fx3, + trig, + fifo_num, + + error, + + test_mode_tpm, + test_mode_tpg, + monitor_error, + + irq, + + fifo0_direction, + fifo0_header_size, + fifo0_buffer_size, + + fifo1_direction, + fifo1_header_size, + fifo1_buffer_size, + + fifo2_direction, + fifo2_header_size, + fifo2_buffer_size, + + fifo3_direction, + fifo3_header_size, + fifo3_buffer_size, + + fifo4_direction, + fifo4_header_size, + fifo4_buffer_size, + + fifo5_direction, + fifo5_header_size, + fifo5_buffer_size, + + fifo6_direction, + fifo6_header_size, + fifo6_buffer_size, + + fifo7_direction, + fifo7_header_size, + fifo7_buffer_size, + + fifo8_direction, + fifo8_header_size, + fifo8_buffer_size, + + fifo9_direction, + fifo9_header_size, + fifo9_buffer_size, + + fifoa_direction, + fifoa_header_size, + fifoa_buffer_size, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // GPIF II + + input [10:0] fifo_rdy; + + input eot_fx32dma; + input eot_dma2fx3; + output trig; + output [ 4:0] fifo_num; + + input error; + + input monitor_error; + output [ 2:0] test_mode_tpm; + output [ 2:0] test_mode_tpg; + + output irq; + + output fifo0_direction; + output [ 7:0] fifo0_header_size; + output [15:0] fifo0_buffer_size; + + output fifo1_direction; + output [ 7:0] fifo1_header_size; + output [15:0] fifo1_buffer_size; + + output fifo2_direction; + output [ 7:0] fifo2_header_size; + output [15:0] fifo2_buffer_size; + + output fifo3_direction; + output [ 7:0] fifo3_header_size; + output [15:0] fifo3_buffer_size; + + output fifo4_direction; + output [ 7:0] fifo4_header_size; + output [15:0] fifo4_buffer_size; + + output fifo5_direction; + output [ 7:0] fifo5_header_size; + output [15:0] fifo5_buffer_size; + + output fifo6_direction; + output [ 7:0] fifo6_header_size; + output [15:0] fifo6_buffer_size; + + output fifo7_direction; + output [ 7:0] fifo7_header_size; + output [15:0] fifo7_buffer_size; + + output fifo8_direction; + output [ 7:0] fifo8_header_size; + output [15:0] fifo8_buffer_size; + + output fifo9_direction; + output [ 7:0] fifo9_header_size; + output [15:0] fifo9_buffer_size; + + output fifoa_direction; + output [ 7:0] fifoa_header_size; + output [15:0] fifoa_buffer_size; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire fifo0_enable; + wire fifo1_enable; + wire fifo2_enable; + wire fifo3_enable; + wire fifo4_enable; + wire fifo5_enable; + wire fifo6_enable; + wire fifo7_enable; + wire fifo8_enable; + wire fifo9_enable; + wire fifoa_enable; + + // internal registers + + reg [31:0] up_rdata = 32'h0; + reg up_rack = 1'b0; + reg up_wack = 1'b0; + + reg [31:0] fifo0_config = 32'h0; + reg [31:0] fifo1_config = 32'h0; + reg [31:0] fifo2_config = 32'h0; + reg [31:0] fifo3_config = 32'h0; + reg [31:0] fifo4_config = 32'h0; + reg [31:0] fifo5_config = 32'h0; + reg [31:0] fifo6_config = 32'h0; + reg [31:0] fifo7_config = 32'h0; + reg [31:0] fifo8_config = 32'h0; + reg [31:0] fifo9_config = 32'h0; + reg [31:0] fifoa_config = 32'h0; + reg [31:0] fifo_status = 32'h0; + reg [31:0] irq_config = 32'h0; // bit 1 - enable error interrupt, bit 0 - enable ready interrupt + reg [31:0] transfer_config = 32'h0; + reg [31:0] transfer_status = 32'h0; + reg [31:0] tpm_config = 32'h0; + reg [31:0] tpm_status = 32'h0; + reg [31:0] tpg_config = 32'h0; + reg [31:0] tpg_status = 32'h0; + + assign up_wreq_s = ((up_waddr[13:8] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == 6'h00)) ? up_rreq : 1'b0; + + assign trig = transfer_config[31]; + assign fifo_num = transfer_config[4:0]; + + assign test_mode_tpm = tpm_config[2:0]; + assign test_mode_tpg = tpg_config[2:0]; + + assign fifo0_enable = fifo0_config[31]; + assign fifo0_direction = fifo0_config[30]; + assign fifo0_header_size = fifo0_config[23:16]; + assign fifo0_buffer_size = fifo0_config[15:0]; + + assign fifo1_enable = fifo1_config[31]; + assign fifo1_direction = fifo1_config[30]; + assign fifo1_header_size = fifo1_config[23:16]; + assign fifo1_buffer_size = fifo1_config[15:0]; + + assign fifo2_enable = fifo2_config[31]; + assign fifo2_direction = fifo2_config[30]; + assign fifo2_header_size = fifo2_config[23:16]; + assign fifo2_buffer_size = fifo2_config[15:0]; + + assign fifo3_enable = fifo3_config[31]; + assign fifo3_direction = fifo3_config[30]; + assign fifo3_header_size = fifo3_config[23:16]; + assign fifo3_buffer_size = fifo3_config[15:0]; + + assign fifo4_enable = fifo4_config[31]; + assign fifo4_direction = fifo4_config[30]; + assign fifo4_header_size = fifo4_config[23:16]; + assign fifo4_buffer_size = fifo4_config[15:0]; + + assign fifo5_enable = fifo5_config[31]; + assign fifo5_direction = fifo5_config[30]; + assign fifo5_header_size = fifo5_config[23:16]; + assign fifo5_buffer_size = fifo5_config[15:0]; + + assign fifo6_enable = fifo6_config[31]; + assign fifo6_direction = fifo6_config[30]; + assign fifo6_header_size = fifo6_config[23:16]; + assign fifo6_buffer_size = fifo6_config[15:0]; + + assign fifo7_enable = fifo7_config[31]; + assign fifo7_direction = fifo7_config[30]; + assign fifo7_header_size = fifo7_config[23:16]; + assign fifo7_buffer_size = fifo7_config[15:0]; + + assign fifo8_enable = fifo8_config[31]; + assign fifo8_direction = fifo8_config[30]; + assign fifo8_header_size = fifo8_config[23:16]; + assign fifo8_buffer_size = fifo8_config[15:0]; + + assign fifo9_enable = fifo9_config[31]; + assign fifo9_direction = fifo9_config[30]; + assign fifo9_header_size = fifo9_config[23:16]; + assign fifo9_buffer_size = fifo9_config[15:0]; + + assign fifoa_enable = fifoa_config[31]; + assign fifoa_direction = fifoa_config[30]; + assign fifoa_header_size = fifoa_config[23:16]; + assign fifoa_buffer_size = fifoa_config[15:0]; + + // generate interrupt if fifo is enabled and fifo is ready + // or if an error has been encountered and irq is enabled + assign irq = ( ((fifo0_enable & fifo_rdy[0]) | (fifo1_enable & fifo_rdy[1]) | + (fifo2_enable & fifo_rdy[2]) | (fifo3_enable & fifo_rdy[3]) | + (fifo4_enable & fifo_rdy[4]) | (fifo5_enable & fifo_rdy[5]) | + (fifo6_enable & fifo_rdy[6]) | (fifo7_enable & fifo_rdy[7]) | + (fifo8_enable & fifo_rdy[8]) | (fifo9_enable & fifo_rdy[9]) | + (fifoa_enable & fifo_rdy[10])) & irq_config[0] ) | (error & irq_config[1] ) ; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + fifo0_config <= 32'h00100400; + fifo1_config <= 32'h00100400; + fifo2_config <= 32'h00100400; + fifo3_config <= 32'h00100400; + fifo4_config <= 32'h00100400; + fifo5_config <= 32'h00100400; + fifo6_config <= 32'h00100400; + fifo7_config <= 32'h00100400; + fifo8_config <= 32'h00100400; + fifo9_config <= 32'h00100400; + fifoa_config <= 32'h00100400; + irq_config <= 32'h0; + transfer_config <= 32'h0; + transfer_status <= 32'h0; + tpm_config <= 32'h0; + tpm_status <= 32'h0; + tpg_config <= 32'h0; + tpg_status <= 32'h0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h0)) begin + fifo0_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + fifo1_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + fifo2_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + fifo3_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + fifo4_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + fifo5_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + fifo6_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + fifo7_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + fifo8_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + fifo9_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + fifoa_config <= up_wdata; + end + fifo_status[10:0] <= fifo_rdy; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + irq_config <= up_wdata; + end + if (eot_fx32dma == 1'b1 || eot_dma2fx3 == 1'b1 || error == 1'b1) begin + transfer_config[31] <= 1'b0; + end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + transfer_config <= up_wdata; + end + if (error == 1'b1) begin + transfer_status[0] <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + transfer_status[0] <= transfer_status[0] & ~up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + tpm_config <= up_wdata; + end + if (monitor_error == 1'b1) begin + tpm_status[0] <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h15)) begin + tpm_status[0] <= tpm_status[0] & ~up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h16)) begin + tpg_config <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h17)) begin + tpg_status <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= fifo0_config; + 5'h1: up_rdata <= fifo1_config; + 5'h2: up_rdata <= fifo2_config; + 5'h3: up_rdata <= fifo3_config; + 5'h4: up_rdata <= fifo4_config; + 5'h5: up_rdata <= fifo5_config; + 5'h6: up_rdata <= fifo6_config; + 5'h7: up_rdata <= fifo7_config; + 5'h8: up_rdata <= fifo8_config; + 5'h9: up_rdata <= fifo9_config; + 5'ha: up_rdata <= fifoa_config; + 5'h10: up_rdata <= fifo_status; + 5'h11: up_rdata <= irq_config; + 5'h12: up_rdata <= transfer_config; + 5'h13: up_rdata <= transfer_status; + 5'h14: up_rdata <= tpm_config; + 5'h15: up_rdata <= tpm_status; + 5'h16: up_rdata <= tpg_config; + 5'h17: up_rdata <= tpg_status; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + +endmodule + +// *************************************************************************** +// ***************************************************************************