From 32dbde69456732530af65e9c49b7fe557939e289 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 19 Mar 2021 08:00:14 +0000 Subject: [PATCH] axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1 This commit removes the deadlock created while trying to use the Rx2/Tx2 channels without the Rx1/Tx1 channels enabled first. --- library/axi_adrv9001/axi_adrv9001_core.v | 18 ++++++++++-------- library/axi_adrv9001/axi_adrv9001_rx.v | 7 +++---- library/axi_adrv9001/axi_adrv9001_tx.v | 7 ++++--- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index d9ef0480d..398185b29 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -186,10 +186,12 @@ module axi_ad9001_core #( wire tx2_data_valid_A; wire [15:0] tx2_data_i_A; wire [15:0] tx2_data_q_A; + wire up_rx1_r1_mode; wire rx1_r1_mode; wire rx2_rst_loc; wire rx2_single_lane_loc; wire rx2_sdr_ddr_n_loc; + wire up_tx1_r1_mode; wire tx1_r1_mode; wire tx2_rst_loc; wire tx2_single_lane_loc; @@ -210,22 +212,22 @@ module axi_ad9001_core #( // tx1_r1_mode should be 0 only when tx1_clk and tx2_clk have the same frequency sync_bits #( - .NUM_OF_BITS (3), + .NUM_OF_BITS (4), .ASYNC_CLK (1)) i_rx1_ctrl_sync ( - .in_bits ({rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), + .in_bits ({up_rx1_r1_mode,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), .out_clk (rx2_clk), .out_resetn (1'b1), - .out_bits ({rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); + .out_bits ({rx1_r1_mode,rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); sync_bits #( - .NUM_OF_BITS (3), + .NUM_OF_BITS (4), .ASYNC_CLK (1)) i_tx1_ctrl_sync ( - .in_bits ({tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), + .in_bits ({up_tx1_r1_mode,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), .out_clk (tx2_clk), .out_resetn (1'b1), - .out_bits ({tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); + .out_bits ({tx1_r1_mode,tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); assign rx2_rst = rx1_r1_mode ? rx2_rst_loc : rx1_rst_s; assign rx2_single_lane = rx1_r1_mode ? rx2_single_lane_loc : rx1_single_lane_s; @@ -312,7 +314,7 @@ module axi_ad9001_core #( .adc_single_lane (rx1_single_lane), .adc_sdr_ddr_n (rx1_sdr_ddr_n), - .adc_r1_mode (rx1_r1_mode), + .up_adc_r1_mode (up_rx1_r1_mode), .adc_clk_ratio (adc_clk_ratio), @@ -431,7 +433,7 @@ module axi_ad9001_core #( .dac_data_q_B (tx1_data_q_B), .dac_single_lane (tx1_single_lane), .dac_sdr_ddr_n (tx1_sdr_ddr_n), - .dac_r1_mode (tx1_r1_mode), + .up_dac_r1_mode (up_tx1_r1_mode), .tdd_tx_valid (tdd_tx1_valid), .dac_clk_ratio (dac_clk_ratio), .dac_sync_in (1'b0), diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v index 5ec8e0b34..c286d669a 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx.v +++ b/library/axi_adrv9001/axi_adrv9001_rx.v @@ -63,7 +63,7 @@ module axi_adrv9001_rx #( output adc_single_lane, output adc_sdr_ddr_n, - output adc_r1_mode, + output up_adc_r1_mode, input [ 31:0] adc_clk_ratio, @@ -110,7 +110,7 @@ if (ENABLED == 0) begin : core_disabled assign adc_rst = 1'b0; assign adc_single_lane = 1'b0; assign adc_sdr_ddr_n = 1'b0; - assign adc_r1_mode = 1'b0; + assign up_adc_r1_mode = 1'b0; assign adc_valid = 1'b0; assign adc_enable_i0 = 1'b0; assign adc_data_i0 = 16'b0; @@ -156,7 +156,6 @@ end else begin : core_enabled wire [ 4:0] up_wack_s; wire [ 4:0] up_rack_s; wire [ 31:0] up_rdata_s[0:4]; - wire up_adc_r1_mode; wire adc_valid_out_i0; wire adc_valid_out_i1; @@ -350,7 +349,7 @@ end else begin : core_enabled .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_r1_mode (adc_r1_mode), + .adc_r1_mode (), .adc_ddr_edgesel (), .adc_pin_mode (), .adc_status (1'b1), diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index f6291a8dc..2188f97e6 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -67,7 +67,7 @@ module axi_adrv9001_tx #( output dac_single_lane, output dac_sdr_ddr_n, - output dac_r1_mode, + output up_dac_r1_mode, input tdd_tx_valid, @@ -116,7 +116,7 @@ if (ENABLED == 0) begin : core_disabled assign dac_data_q_B = 16'b0; assign dac_single_lane = 1'b0; assign dac_sdr_ddr_n = 1'b0; - assign dac_r1_mode = 1'b0; + assign up_dac_r1_mode = 1'b0; assign dac_sync_out = 1'b0; assign dac_valid = 1'b0; assign dac_enable_i0 = 1'b0; @@ -375,7 +375,8 @@ end else begin : core_enabled .dac_clksel (), .dac_par_type (), .dac_par_enb (), - .dac_r1_mode (dac_r1_mode), + .dac_r1_mode (), + .up_dac_r1_mode (up_dac_r1_mode), .dac_datafmt (dac_dds_format_s), .dac_datarate (dac_datarate_s), .dac_status (1'b1),