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ad9361: add ddr-edgesel

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Rejeesh Kutty 2015-05-06 16:57:58 -04:00
parent 670850183b
commit 32f7e98afd
1 changed files with 3 additions and 0 deletions
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library/axi_ad9361/axi_ad9361.v
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@ -269,6 +269,7 @@ module axi_ad9361 (
// internal signals
wire adc_ddr_edgesel;
wire adc_valid_s;
wire [47:0] adc_data_s;
wire adc_status_s;
@ -337,6 +338,7 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_r1_mode (dac_r1_mode),
@ -364,6 +366,7 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.dac_data (dac_data_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),