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axi_ad7616: Delete burst_length register 

This was an unnecessary feature of the hdl core.
main
Istvan Csomortani 2016-04-29 16:28:48 +03:00
parent d5d7c12f0e
commit 33199263e1
3 changed files with 6 additions and 32 deletions
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3
library/axi_ad7616/axi_ad7616.v
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@ -178,7 +178,6 @@ module axi_ad7616 (
wire [15:0] wr_data_s; wire [15:0] wr_data_s;
wire [15:0] rd_data_s; wire [15:0] rd_data_s;
wire rd_valid_s; wire rd_valid_s;
wire [ 4:0] burst_length_s;
wire m_axis_ready_s; wire m_axis_ready_s;
@ -434,7 +433,6 @@ module axi_ad7616 (
.m_axis_tready(m_axis_ready_s), .m_axis_tready(m_axis_ready_s),
.m_axis_xfer_req(m_axis_xfer_req), .m_axis_xfer_req(m_axis_xfer_req),
.end_of_conv(trigger_s), .end_of_conv(trigger_s),
.burst_length(burst_length_s),
.clk(up_clk), .clk(up_clk),
.rstn(up_rstn), .rstn(up_rstn),
.rd_req(rd_req_s), .rd_req(rd_req_s),
@ -453,7 +451,6 @@ module axi_ad7616 (
) i_ad7616_control ( ) i_ad7616_control (
.cnvst (cnvst), .cnvst (cnvst),
.busy (busy), .busy (busy),
.up_burst_length (burst_length_s),
.up_read_data (rd_data_s), .up_read_data (rd_data_s),
.up_read_valid (rd_valid_s), .up_read_valid (rd_valid_s),
.up_write_data (wr_data_s), .up_write_data (wr_data_s),

19
library/axi_ad7616/axi_ad7616_control.v
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@ -52,7 +52,6 @@ module axi_ad7616_control (
up_read_req, up_read_req,
up_write_req, up_write_req,
up_burst_length,
end_of_conv, end_of_conv,
// bus interface // bus interface
@ -83,7 +82,6 @@ module axi_ad7616_control (
input busy; input busy;
output end_of_conv; output end_of_conv;
output [ 4:0] up_burst_length;
input [15:0] up_read_data; input [15:0] up_read_data;
input up_read_valid; input up_read_valid;
@ -113,7 +111,6 @@ module axi_ad7616_control (
reg up_rack = 1'b0; reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0; reg [31:0] up_rdata = 32'b0;
reg [31:0] up_conv_rate = 32'b0; reg [31:0] up_conv_rate = 32'b0;
reg [ 4:0] up_burst_length = 5'h0;
reg [15:0] up_write_data = 16'h0; reg [15:0] up_write_data = 16'h0;
reg [31:0] cnvst_counter = 32'b0; reg [31:0] cnvst_counter = 32'b0;
@ -149,7 +146,6 @@ module axi_ad7616_control (
up_resetn <= 1'b0; up_resetn <= 1'b0;
up_cnvst_en <= 1'b0; up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0; up_conv_rate <= 32'b0;
up_burst_length <= 5'h0;
end else begin end else begin
up_wack <= up_wreq_s; up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -162,20 +158,18 @@ module axi_ad7616_control (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_conv_rate <= up_wdata; up_conv_rate <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_burst_length <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_write_data <= up_wdata; up_write_data <= up_wdata;
end end
end end
end end
assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0; assign up_write_req = (up_waddr[7:0] == 8'h13) ? up_wreq_s : 1'h0;
// processor read interface // processor read interface
assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s; assign up_rack_s = (up_raddr[7:0] == 8'h12) ? up_read_valid_s : up_rreq_s;
assign up_read_req = (up_raddr[7:0] == 8'h12) ? up_rreq_s : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
@ -190,15 +184,12 @@ module axi_ad7616_control (
8'h02 : up_rdata = up_scratch; 8'h02 : up_rdata = up_scratch;
8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn}; 8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
8'h11 : up_rdata = up_conv_rate; 8'h11 : up_rdata = up_conv_rate;
8'h12 : up_rdata = {27'b0, up_burst_length}; 8'h12 : up_rdata = up_read_data_s;
8'h13 : up_rdata = up_read_data_s;
endcase endcase
end end
end end
end end
assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
// instantiations // instantiations
assign up_rst = ~up_rstn; assign up_rst = ~up_rstn;

16
library/axi_ad7616/axi_ad7616_pif.v
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@ -60,7 +60,6 @@ module axi_ad7616_pif (
// end of convertion // end of convertion
end_of_conv, end_of_conv,
burst_length,
// register access // register access
@ -85,7 +84,6 @@ module axi_ad7616_pif (
output wr_n; output wr_n;
input end_of_conv; input end_of_conv;
input [ 4:0] burst_length;
input clk; input clk;
input rstn; input rstn;
@ -115,7 +113,6 @@ module axi_ad7616_pif (
reg [ 2:0] transfer_state = 3'h0; reg [ 2:0] transfer_state = 3'h0;
reg [ 2:0] transfer_state_next = 3'h0; reg [ 2:0] transfer_state_next = 3'h0;
reg [ 1:0] width_counter = 2'h0; reg [ 1:0] width_counter = 2'h0;
reg [ 4:0] burst_counter = 5'h0;
reg wr_req_d = 1'h0; reg wr_req_d = 1'h0;
reg rd_req_d = 1'h0; reg rd_req_d = 1'h0;
@ -159,17 +156,6 @@ module axi_ad7616_pif (
end end
end end
always @(posedge clk) begin
if (rstn == 1'b0) begin
burst_counter <= 2'h0;
end else begin
if((transfer_state == CS_HIGH) && (rd_conv_d == 1'b1))
burst_counter <= burst_counter + 1;
else if (transfer_state == IDLE)
burst_counter <= 5'h0;
end
end
always @(negedge clk) begin always @(negedge clk) begin
if (transfer_state == IDLE) begin if (transfer_state == IDLE) begin
wr_req_d <= wr_req; wr_req_d <= wr_req;
@ -202,7 +188,7 @@ module axi_ad7616_pif (
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH; transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
end end
CS_HIGH : begin CS_HIGH : begin
transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW; transfer_state_next <= IDLE;
end end
default : begin default : begin
transfer_state_next <= IDLE; transfer_state_next <= IDLE;