From 334ce5ddc0cfca4fa45ff21f616435d94338baea Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 2 Dec 2016 15:33:35 +0100 Subject: [PATCH] axi_intr_monitor: Fully register IRQ output signal The IRQ signal goes to a asynchronous domain. In order to avoid glitches to be observed in that domain make sure that the output signal is fully registered. This means that the IRQ signal is no longer mask when the control enable bit is not set. Instead modify the code to clear the interrupt when the control enable bit is not set. This turns it into a true reset for the internal state. Signed-off-by: Lars-Peter Clausen --- library/axi_intr_monitor/axi_intr_monitor.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v index c071fc588..07e65c5c5 100644 --- a/library/axi_intr_monitor/axi_intr_monitor.v +++ b/library/axi_intr_monitor/axi_intr_monitor.v @@ -105,7 +105,7 @@ wire [31:0] up_wdata_s; //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ -assign irq = interrupt & control[0]; +assign irq = interrupt; always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin @@ -152,10 +152,12 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin control <= up_wdata_s; end - if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin + if (control[0] == 1'b0) begin + interrupt <= 1'b0; + end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin interrupt <= interrupt & ~up_wdata_s[0]; end else begin - if (counter_to_interrupt_cnt == 32'h0 && control[0] == 1'b1) begin + if (counter_to_interrupt_cnt == 32'h0) begin interrupt <= 1'b1; end end