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axi_intr_monitor: Fully register IRQ output signal 

The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.

This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2016-12-02 15:33:35 +01:00
parent 170c781d02
commit 334ce5ddc0
1 changed files with 5 additions and 3 deletions
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8
library/axi_intr_monitor/axi_intr_monitor.v
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@ -105,7 +105,7 @@ wire [31:0] up_wdata_s;
//----------- Assign/Always Blocks --------------------------------------------- //----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
assign irq = interrupt & control[0]; assign irq = interrupt;
always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
@ -152,10 +152,12 @@ always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
control <= up_wdata_s; control <= up_wdata_s;
end end
if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin if (control[0] == 1'b0) begin
interrupt <= 1'b0;
end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
interrupt <= interrupt & ~up_wdata_s[0]; interrupt <= interrupt & ~up_wdata_s[0];
end else begin end else begin
if (counter_to_interrupt_cnt == 32'h0 && control[0] == 1'b1) begin if (counter_to_interrupt_cnt == 32'h0) begin
interrupt <= 1'b1; interrupt <= 1'b1;
end end
end end