From 3436210429d16a4305e1ab7a8b8be34cb024c43d Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 30 Mar 2018 17:55:22 +0300 Subject: [PATCH] axi_adcfifo: Infer clock and reset signals --- library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl index 3652552d1..d6e919f35 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl @@ -79,5 +79,9 @@ set_property range 4294967296 [ipx::get_address_spaces axi \ set_property width 512 [ipx::get_address_spaces axi \ -of_objects [ipx::current_core]] +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::save_core [ipx::current_core]