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axi_adcfifo: Infer clock and reset signals

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Adrian Costina 2018-03-30 17:55:22 +03:00 committed by István Csomortáni
parent b7f8345f17
commit 3436210429
1 changed files with 4 additions and 0 deletions
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4
library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl
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@ -79,5 +79,9 @@ set_property range 4294967296 [ipx::get_address_spaces axi \
set_property width 512 [ipx::get_address_spaces axi \
-of_objects [ipx::current_core]]
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]