From 34ffa15b12cc66941f0dd7989bae4a7415b1d0dc Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 4 Dec 2014 15:39:17 +0200 Subject: [PATCH] zynq_plddr3: Fix PLDDR3's Reset Generator Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset. Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to set this two property of the reset generator. --- projects/common/zc706/zc706_system_plddr3.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index d2e124c7c..cd1b2b87e 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -36,7 +36,8 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen] - + set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen + set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s] set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_fifo2s