diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
index 31601141d..88fa70f67 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
@@ -130,19 +130,7 @@ wire up_cfg_is_writeable;
 
 wire [4:0] up_irq_trigger;
 
-sync_event #(
-  .NUM_OF_EVENTS(2)
-) i_sync_events (
-  .in_clk(core_clk),
-  .in_event({
-    core_event_sysref_alignment_error,
-    core_event_sysref_edge
-  }),
-  .out_clk(s_axi_aclk),
-  .out_event(up_irq_trigger[1:0])
-);
-
-assign up_irq_trigger[4:2] = 3'b000;
+assign up_irq_trigger[4:0] = 5'b00000;
 
 up_axi #(
   .AXI_ADDRESS_WIDTH (14),
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
index 40eefb9ea..dcb9ba9f8 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
@@ -81,19 +81,6 @@ set_max_delay -datapath_only \
   -to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \
   [get_property -min PERIOD $axi_clk]
 
-set_false_path \
-  -from [get_pins {i_sync_events/out_toggle_d1_reg/C}]  \
-  -to [get_pins {i_sync_events/i_sync_in/cdc_sync_stage1_reg[0]/D}]
-
-set_false_path \
-  -from [get_pins {i_sync_events/in_toggle_d1_reg/C}] \
-  -to [get_pins {i_sync_events/i_sync_out/cdc_sync_stage1_reg[0]/D}]
-
-set_max_delay -datapath_only \
-  -from [get_pins {i_sync_events/cdc_hold_reg[*]/C}] \
-  -to [get_pins {i_sync_events/out_event_reg[*]/D}] \
-  [get_property -min PERIOD $axi_clk]
-
 set_false_path \
   -from $core_clk \
   -to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}]