axi_jesd204_tx: Remove IRQ events for now
Which events will be exposed as IRQs and at what level of granularity will need some additional through. Remove the two existing IRQ events for now again. This will be added back later. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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533b27bb13
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350fbacf94
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@ -130,19 +130,7 @@ wire up_cfg_is_writeable;
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wire [4:0] up_irq_trigger;
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wire [4:0] up_irq_trigger;
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sync_event #(
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assign up_irq_trigger[4:0] = 5'b00000;
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.NUM_OF_EVENTS(2)
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) i_sync_events (
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.in_clk(core_clk),
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.in_event({
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core_event_sysref_alignment_error,
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core_event_sysref_edge
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}),
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.out_clk(s_axi_aclk),
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.out_event(up_irq_trigger[1:0])
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);
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assign up_irq_trigger[4:2] = 3'b000;
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up_axi #(
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up_axi #(
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.AXI_ADDRESS_WIDTH (14),
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.AXI_ADDRESS_WIDTH (14),
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@ -81,19 +81,6 @@ set_max_delay -datapath_only \
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-to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \
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-to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \
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[get_property -min PERIOD $axi_clk]
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[get_property -min PERIOD $axi_clk]
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set_false_path \
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-from [get_pins {i_sync_events/out_toggle_d1_reg/C}] \
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-to [get_pins {i_sync_events/i_sync_in/cdc_sync_stage1_reg[0]/D}]
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set_false_path \
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-from [get_pins {i_sync_events/in_toggle_d1_reg/C}] \
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-to [get_pins {i_sync_events/i_sync_out/cdc_sync_stage1_reg[0]/D}]
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set_max_delay -datapath_only \
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-from [get_pins {i_sync_events/cdc_hold_reg[*]/C}] \
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-to [get_pins {i_sync_events/out_event_reg[*]/D}] \
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[get_property -min PERIOD $axi_clk]
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set_false_path \
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set_false_path \
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-from $core_clk \
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-from $core_clk \
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-to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}]
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-to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}]
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