From 3516c4ca83090ecd318973402499d1e128b4fd35 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 5 May 2017 18:53:39 +0200 Subject: [PATCH] library: Add a generic JESD204 ADC receiver core For most of the ADCs that use JESD204 as the data transport the digitial interface is very similar. They are mainly differentiated by number of JESD204 lanes, number of converter channels and number of bits per sample. Currently for each supported converter there exists a converter specific core which has the converter specific requirements hard-coded. Introduce a new generic core that has the number of lanes, number of channels and bits per sample as synthesis-time configurable parameters. It can be used as a drop-in replacement for the existing converter specific cores. This has the advantage of a shared and reduced code base. Code improvements will automatically be available for all converters and don't have to be manually ported to each core individually. It also makes it very easy to introduce support for new converters that follow the existing schema. Since the JESD204 deframer is now procedurally generated it is also very easy to support board or application specific requirements where the lane to converter ratio differs from the default (E.g. use 2 lanes/2 converters instead of 4 lanes/2 converters). This new core is primarily based on the existing axi_ad9680. For the time being the core is not user instantiatable and will only be used as a based to re-implement the converter specific cores. It will be extended in the future to allow user instantiation. Signed-off-by: Lars-Peter Clausen --- library/Makefile | 2 + .../jesd204/ad_ip_jesd204_tpl_adc/Makefile | 31 ++ .../ad_ip_jesd204_tpl_adc.v | 161 ++++++++++ .../ad_ip_jesd204_tpl_adc_channel.v | 82 +++++ .../ad_ip_jesd204_tpl_adc_core.v | 95 ++++++ .../ad_ip_jesd204_tpl_adc_deframer.v | 86 +++++ .../ad_ip_jesd204_tpl_adc_ip.tcl | 55 ++++ .../ad_ip_jesd204_tpl_adc_pnmon.v | 106 +++++++ .../ad_ip_jesd204_tpl_adc_regmap.v | 293 ++++++++++++++++++ 9 files changed, 911 insertions(+) create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/Makefile create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v create mode 100644 library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v diff --git a/library/Makefile b/library/Makefile index 7a0246d65..9f31c6ba9 100644 --- a/library/Makefile +++ b/library/Makefile @@ -67,6 +67,7 @@ clean: $(MAKE) -C cn0363/cn0363_dma_sequencer clean $(MAKE) -C cn0363/cn0363_phase_data_sync clean $(MAKE) -C cordic_demod clean + $(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean $(MAKE) -C jesd204/axi_jesd204_common clean $(MAKE) -C jesd204/axi_jesd204_rx clean $(MAKE) -C jesd204/axi_jesd204_tx clean @@ -173,6 +174,7 @@ lib: $(MAKE) -C cn0363/cn0363_dma_sequencer $(MAKE) -C cn0363/cn0363_phase_data_sync $(MAKE) -C cordic_demod + $(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc $(MAKE) -C jesd204/axi_jesd204_common $(MAKE) -C jesd204/axi_jesd204_rx $(MAKE) -C jesd204/axi_jesd204_tx diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile b/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile new file mode 100644 index 000000000..5a0835223 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := ad_ip_jesd204_tpl_adc + +GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v + +XILINX_DEPS += ../../common/ad_datafmt.v +XILINX_DEPS += ../../common/ad_pnmon.v +XILINX_DEPS += ../../common/ad_rst.v +XILINX_DEPS += ../../common/ad_xcvr_rx_if.v +XILINX_DEPS += ../../common/up_adc_channel.v +XILINX_DEPS += ../../common/up_adc_common.v +XILINX_DEPS += ../../common/up_axi.v +XILINX_DEPS += ../../common/up_clock_mon.v +XILINX_DEPS += ../../common/up_xfer_cntrl.v +XILINX_DEPS += ../../common/up_xfer_status.v +XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl + +include ../../scripts/library.mk diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v new file mode 100644 index 000000000..c9c94d30a --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc #( + parameter ID = 0, + parameter NUM_CHANNELS = 1, + parameter CHANNEL_WIDTH = 14, + parameter NUM_LANES = 1, + parameter TWOS_COMPLEMENT = 1 +) ( + // jesd interface + // link_clk is (line-rate/40) + input link_clk, + + input [3:0] link_sof, + input link_valid, + input [NUM_LANES*32-1:0] link_data, + output link_ready, + + // dma interface + + output [NUM_CHANNELS-1:0] enable, + + output [NUM_CHANNELS-1:0] adc_valid, + output [NUM_LANES*32-1:0] adc_data, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + output s_axi_awready, + input [15:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + + input s_axi_wvalid, + output s_axi_wready, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + + output s_axi_bvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + + input s_axi_arvalid, + output s_axi_arready, + input [15:0] s_axi_araddr, + input [2:0] s_axi_arprot, + + output s_axi_rvalid, + input s_axi_rready, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata +); + + // Number of samples per channel that are processed in parallel. + // Assumes 2 octets per sample. + localparam DATA_PATH_WIDTH = 2 * NUM_LANES / NUM_CHANNELS; + + wire [NUM_CHANNELS-1:0] dfmt_enable_s; + wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s; + wire [NUM_CHANNELS-1:0] dfmt_type_s; + + wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s; + wire [NUM_CHANNELS-1:0] pn_err_s; + wire [NUM_CHANNELS-1:0] pn_oos_s; + + // regmap + ad_ip_jesd204_tpl_adc_regmap #( + .ID (ID), + .NUM_CHANNELS (NUM_CHANNELS), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + ) i_regmap ( + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata), + + .link_clk (link_clk), + + .dfmt_enable (dfmt_enable_s), + .dfmt_sign_extend (dfmt_sign_extend_s), + .dfmt_type (dfmt_type_s), + + .pn_seq_sel (pn_seq_sel_s), + .pn_err (pn_err_s), + .pn_oos (pn_oos_s), + + .enable (enable), + + .adc_dovf (adc_dovf) + ); + + ad_ip_jesd204_tpl_adc_core #( + .NUM_CHANNELS (NUM_CHANNELS), + .CHANNEL_WIDTH (CHANNEL_WIDTH), + .NUM_LANES (NUM_LANES), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + ) i_core ( + .clk (link_clk), + + .dfmt_enable (dfmt_enable_s), + .dfmt_sign_extend (dfmt_sign_extend_s), + .dfmt_type (dfmt_type_s), + + .pn_seq_sel (pn_seq_sel_s), + .pn_err (pn_err_s), + .pn_oos (pn_oos_s), + + .link_valid (link_valid), + .link_ready (link_ready), + .link_sof (link_sof), + .link_data (link_data), + + .adc_valid (adc_valid), + .adc_data (adc_data) + ); + +endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v new file mode 100644 index 000000000..4d79fd36f --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v @@ -0,0 +1,82 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_channel #( + parameter CHANNEL_WIDTH = 14, + parameter DATA_PATH_WIDTH = 2, + parameter TWOS_COMPLEMENT = 1 +) ( + input clk, + + input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] raw_data, + + output [16*DATA_PATH_WIDTH-1:0] fmt_data, + + // Configuration and status + input dfmt_enable, + input dfmt_type, + input dfmt_sign_extend, + + input [3:0] pn_seq_sel, + output pn_oos, + output pn_err +); + + // instantiations + + ad_ip_jesd204_tpl_adc_pnmon #( + .CHANNEL_WIDTH (CHANNEL_WIDTH), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT) + ) i_pnmon ( + .clk (clk), + .data (raw_data), + + .pn_seq_sel (pn_seq_sel), + .pn_oos (pn_oos), + .pn_err (pn_err) + ); + + generate + genvar n; + for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin: g_datafmt + ad_datafmt #( + .DATA_WIDTH (CHANNEL_WIDTH) + ) i_ad_datafmt ( + .clk (clk), + + .valid (1'b1), + .data (raw_data[n*CHANNEL_WIDTH+:CHANNEL_WIDTH]), + .valid_out (), + .data_out (fmt_data[n*16+:16]), + + .dfmt_enable (dfmt_enable), + .dfmt_type (dfmt_type), + .dfmt_se (dfmt_sign_extend) + ); + end + endgenerate + +endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v new file mode 100644 index 000000000..cfa2e89e9 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v @@ -0,0 +1,95 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_core #( + parameter NUM_CHANNELS = 1, + parameter CHANNEL_WIDTH = 14, + parameter NUM_LANES = 1, + parameter TWOS_COMPLEMENT = 1, + parameter DATA_PATH_WIDTH = 1 +) ( + input clk, + + input [NUM_CHANNELS-1:0] dfmt_enable, + input [NUM_CHANNELS-1:0] dfmt_sign_extend, + input [NUM_CHANNELS-1:0] dfmt_type, + + input [NUM_CHANNELS*4-1:0] pn_seq_sel, + output [NUM_CHANNELS-1:0] pn_err, + output [NUM_CHANNELS-1:0] pn_oos, + + output [NUM_CHANNELS-1:0] adc_valid, + output [NUM_LANES*32-1:0] adc_data, + + input link_valid, + output link_ready, + input [3:0] link_sof, + input [NUM_LANES*32-1:0] link_data +); + // Raw and formated channel data widths + localparam CDW_RAW = CHANNEL_WIDTH * DATA_PATH_WIDTH; + localparam CDW_FMT = 16 * DATA_PATH_WIDTH; + + wire [NUM_CHANNELS*CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] raw_data_s; + + assign link_ready = 1'b1; + assign adc_valid = {NUM_CHANNELS{1'b1}}; + + ad_ip_jesd204_tpl_adc_deframer #( + .NUM_LANES (NUM_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .CHANNEL_WIDTH (CHANNEL_WIDTH) + ) i_deframer ( + .clk (clk), + .link_sof (link_sof), + .link_data (link_data), + .adc_data (raw_data_s) + ); + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + ad_ip_jesd204_tpl_adc_channel #( + .CHANNEL_WIDTH (CHANNEL_WIDTH), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT) + ) i_channel ( + .clk (clk), + + .raw_data (raw_data_s[CDW_RAW*i+:CDW_RAW]), + .fmt_data (adc_data[CDW_FMT*i+:CDW_FMT]), + + .dfmt_enable (dfmt_enable[i]), + .dfmt_sign_extend (dfmt_sign_extend[i]), + .dfmt_type (dfmt_type[i]), + + .pn_seq_sel (pn_seq_sel[i*4+:4]), + .pn_err (pn_err[i]), + .pn_oos (pn_oos[i]) + ); + end + endgenerate + +endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v new file mode 100644 index 000000000..a997e0c33 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v @@ -0,0 +1,86 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_deframer #( + parameter NUM_LANES = 1, + parameter NUM_CHANNELS = 1, + parameter CHANNEL_WIDTH = 16 +) ( + // jesd interface + // clk is (line-rate/40) + + input clk, + input [3:0] link_sof, + input [NUM_LANES*32-1:0] link_data, + + // adc data output + + output [NUM_LANES*CHANNEL_WIDTH*2-1:0] adc_data + ); + + localparam TAIL_BITS = (16 - CHANNEL_WIDTH); + localparam DATA_PATH_WIDTH = 2 * NUM_LANES / NUM_CHANNELS; + localparam H = NUM_LANES / NUM_CHANNELS / 2; + localparam HD = NUM_LANES > NUM_CHANNELS ? 1 : 0; + localparam OCT_OFFSET = HD ? 32 : 8; + + wire [NUM_LANES*32-1:0] link_data_s; + + // data multiplex + + genvar i; + genvar j; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_deframer_outer + for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin: g_deframer_inner + localparam k = j + i * DATA_PATH_WIDTH; + localparam adc_lsb = k * CHANNEL_WIDTH; + localparam oct0_lsb = HD ? ((i * H + j % H) * 64 + (j / H) * 8) : (k * 16); + localparam oct1_lsb = oct0_lsb + OCT_OFFSET + TAIL_BITS; + + assign adc_data[adc_lsb+:CHANNEL_WIDTH] = { + link_data_s[oct0_lsb+:8], + link_data_s[oct1_lsb+:8-TAIL_BITS] + }; + end + end + endgenerate + + // frame-alignment + + generate + genvar n; + for (n = 0; n < NUM_LANES; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if i_xcvr_if ( + .rx_clk (clk), + .rx_ip_sof (link_sof), + .rx_ip_data (link_data[n*32+:32]), + .rx_sof (), + .rx_data (link_data_s[n*32+:32]) + ); + end + endgenerate + +endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl new file mode 100644 index 000000000..fa1f0eb20 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl @@ -0,0 +1,55 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# +# Each core or library found in this collection may have its own licensing terms. +# The user should keep this in in mind while exploring these cores. +# +# Redistribution and use in source and binary forms, +# with or without modification of this file, are permitted under the terms of either +# (at the option of the user): +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory, or at: +# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +# +# OR +# +# 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +# +# *************************************************************************** +# *************************************************************************** + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create ad_ip_jesd204_tpl_adc +adi_ip_files ad_ip_jesd204_tpl_adc [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "ad_ip_jesd204_tpl_adc_core.v" \ + "ad_ip_jesd204_tpl_adc_channel.v" \ + "ad_ip_jesd204_tpl_adc_deframer.v" \ + "ad_ip_jesd204_tpl_adc_pnmon.v" \ + "ad_ip_jesd204_tpl_adc_regmap.v" \ + "ad_ip_jesd204_tpl_adc.v" \ + ] + +adi_ip_properties ad_ip_jesd204_tpl_adc + +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v new file mode 100644 index 000000000..0aef9f030 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v @@ -0,0 +1,106 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_pnmon #( + parameter CHANNEL_WIDTH = 16, + parameter DATA_PATH_WIDTH = 1, + parameter TWOS_COMPLEMENT = 1 +) ( + input clk, + + // data interface + input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] data, + + // pn out of sync and error + output pn_oos, + output pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + input [3:0] pn_seq_sel +); + + localparam DW = DATA_PATH_WIDTH*CHANNEL_WIDTH-1; + + // internal registers + reg [DW:0] pn_data_pn = 'd0; + + // internal signals + wire [DW:0] pn_data_pn_s; + wire [DW:0] pn_data_in_s; + + wire [DW:0] pn23; + wire [DW+23:0] full_state_pn23; + wire [DW:0] pn9; + wire [DW+9:0] full_state_pn9; + + // pn sequence select + + assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_in_s : pn_data_pn; + + wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0; + + generate + genvar i; + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle + localparam src_lsb = i * CHANNEL_WIDTH; + localparam src_msb = src_lsb + CHANNEL_WIDTH - 1; + localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CHANNEL_WIDTH; + localparam dst_msb = dst_lsb + CHANNEL_WIDTH - 1; + + assign pn_data_in_s[dst_msb] = tc ^ data[src_msb]; + assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb]; + end + endgenerate + + // PN23 x^23 + x^18 + 1 + assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1]; + assign full_state_pn23 = {pn_data_pn_s[22:0],pn23}; + + // PN9 x^9 + x^5 + 1 + assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1]; + assign full_state_pn9 = {pn_data_pn_s[8:0],pn9}; + + always @(posedge clk) begin + if (pn_seq_sel == 4'd0) begin + pn_data_pn <= pn9; + end else begin + pn_data_pn <= pn23; + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH (DW+1) + ) i_pnmon ( + .adc_clk (clk), + .adc_valid_in (1'b1), + .adc_data_in (pn_data_in_s), + .adc_data_pn (pn_data_pn), + .adc_pn_oos (pn_oos), + .adc_pn_err (pn_err) + ); + +endmodule diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v new file mode 100644 index 000000000..76ef58298 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -0,0 +1,293 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + + + +module ad_ip_jesd204_tpl_adc_regmap #( + parameter ID = 0, + parameter NUM_CHANNELS = 1, + parameter DATA_PATH_WIDTH = 1 +) ( + // axi interface + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // control interface + input link_clk, + + // Data format conversion configuration + output [NUM_CHANNELS-1:0] dfmt_enable, + output [NUM_CHANNELS-1:0] dfmt_sign_extend, + output [NUM_CHANNELS-1:0] dfmt_type, + + // PN sequence monitor + output [NUM_CHANNELS*4-1:0] pn_seq_sel, + input [NUM_CHANNELS-1:0] pn_err, + input [NUM_CHANNELS-1:0] pn_oos, + + output [NUM_CHANNELS-1:0] enable, + + // Underflow + input adc_dovf +); + + localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH; + + reg up_rack = 1'b0; + reg up_wack = 1'b0; + reg [31:0] up_rdata = 32'h00; + reg [31:0] up_rdata_all; + + reg up_status_pn_err = 1'b0; + reg up_status_pn_oos = 1'b0; + + reg adc_status = 1'b0; + + // internal clocks & resets + wire up_clk; + wire up_rstn; + + wire adc_rst; + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [NUM_CHANNELS:0] up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:NUM_CHANNELS]; + wire [NUM_CHANNELS:0] up_rack_s; + + wire [NUM_CHANNELS-1:0] up_adc_pn_err_s; + wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // status + + always @(posedge link_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack) + ); + + integer n; + + always @(*) begin + up_rdata_all = 'h00; + for (n = 0; n <= NUM_CHANNELS; n = n + 1) begin + up_rdata_all = up_rdata_all | up_rdata_s[n]; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= |up_adc_pn_err_s; + up_status_pn_oos <= |up_adc_pn_oos_s; + + up_rdata <= up_rdata_all; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; + end + end + + // common processor control + + up_adc_common #( + .ID (ID), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (1), + .GPIO_DISABLE (1), + .START_CODE_DISABLE (1) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (link_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (CLK_RATIO), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (1'b0), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_adc_ce (), + .up_pps_rcounter (32'd0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0]) + ); + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + up_adc_channel #( + .CHANNEL_ID (i), + .USERPORTS_DISABLE (1), + .DCFILTER_DISABLE (1), + .IQCORRECTION_DISABLE (1) + ) i_up_adc_channel ( + .adc_clk (link_clk), + .adc_rst (adc_rst), + .adc_enable (enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_enable (dfmt_enable[i]), + .adc_dfmt_se (dfmt_sign_extend[i]), + .adc_dfmt_type (dfmt_type[i]), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (pn_seq_sel[i*4+:4]), + .adc_data_sel (), + .adc_pn_err (pn_err[i]), + .adc_pn_oos (pn_oos[i]), + .adc_or (1'b0), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + + .up_adc_pn_err (up_adc_pn_err_s[i]), + .up_adc_pn_oos (up_adc_pn_oos_s[i]), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i+1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i+1]), + .up_rack (up_rack_s[i+1]) + ); + end + endgenerate + +endmodule