diff --git a/projects/ad469x_fmc/Makefile b/projects/ad469x_fmc/Makefile new file mode 100644 index 000000000..4af18d6e7 --- /dev/null +++ b/projects/ad469x_fmc/Makefile @@ -0,0 +1,6 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad469x_fmc/common/ad469x_bd.tcl b/projects/ad469x_fmc/common/ad469x_bd.tcl new file mode 100644 index 000000000..ebf511508 --- /dev/null +++ b/projects/ad469x_fmc/common/ad469x_bd.tcl @@ -0,0 +1,95 @@ + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad469x_spi +create_bd_port -dir O ad469x_spi_cnv +create_bd_port -dir I ad469x_spi_busy + +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +set data_width $ad_project_params(DATA_WIDTH) +set async_spi_clk $ad_project_params(ASYNC_SPI_CLK) +set num_cs $ad_project_params(NUM_CS) +set num_sdi $ad_project_params(NUM_SDI) +set sdi_delay $ad_project_params(SDI_DELAY) + +set hier_spi_engine spi_ad469x + +spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay + +# To support the 1MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz + +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 + +## to setup the sample rate of the system change the PULSE_PERIOD value +## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk) +set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $adc_sampling_rate))] + +ad_ip_instance axi_pulse_gen ad469x_trigger_gen + +ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle +ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_WIDTH 1 + +ad_connect spi_clk ad469x_trigger_gen/ext_clk +ad_connect $sys_cpu_clk ad469x_trigger_gen/s_axi_aclk +ad_connect sys_cpu_resetn ad469x_trigger_gen/s_axi_aresetn + +# trigger to BUSY's negative edge + +create_bd_cell -type module -reference sync_bits busy_sync +create_bd_cell -type module -reference ad_edge_detect busy_capture +set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture] + +ad_connect spi_clk busy_capture/clk +ad_connect busy_capture/rst GND + +ad_connect busy_sync/out_resetn $hier_spi_engine/axi_regmap/spi_resetn +ad_connect spi_clk busy_sync/out_clk +ad_connect busy_sync/in_bits ad469x_spi_busy +ad_connect busy_sync/out_bits busy_capture/in +ad_connect busy_capture/out $hier_spi_engine/offload/trigger + +# dma to receive data stream + +ad_ip_instance axi_dmac axi_ad469x_dma +ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad469x_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad469x_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad469x_dma CONFIG.DMA_2D_TRANSFER 0 + +ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width +ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect sys_cpu_clk $hier_spi_engine/clk +ad_connect spi_clk axi_ad469x_dma/s_axis_aclk +ad_connect sys_cpu_resetn $hier_spi_engine/resetn +ad_connect sys_cpu_resetn axi_ad469x_dma/m_dest_axi_aresetn + +ad_connect spi_clk $hier_spi_engine/spi_clk +ad_connect $hier_spi_engine/m_spi ad469x_spi +ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE + +ad_ip_instance util_vector_logic cnv_gate +ad_ip_parameter cnv_gate CONFIG.C_SIZE 1 +ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and} + +ad_connect cnv_gate/Op1 axi_ad469x_dma/s_axis_xfer_req +ad_connect cnv_gate/Op2 ad469x_trigger_gen/pulse +ad_connect cnv_gate/Res ad469x_spi_cnv + +ad_cpu_interconnect 0x44a00000 $hier_spi_engine/axi_regmap +ad_cpu_interconnect 0x44a30000 axi_ad469x_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen +ad_cpu_interconnect 0x44b00000 ad469x_trigger_gen + +ad_cpu_interrupt "ps-13" "mb-13" axi_ad469x_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq + +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad469x_dma/m_dest_axi diff --git a/projects/ad469x_fmc/common/config.tcl b/projects/ad469x_fmc/common/config.tcl new file mode 100644 index 000000000..8f9953c96 --- /dev/null +++ b/projects/ad469x_fmc/common/config.tcl @@ -0,0 +1,25 @@ + +set device AD469X +set mode 0 + +set hier_spi_engine spi_ad469x + +if [info exists ::env(ADI_DAC_MODE)] { + set mode $::env(ADI_DAC_MODE) +} else { + set env(ADI_DAC_MODE) $mode +} + +# W A NC NS D +set params(AD469X,0) {32 1 1 1 1} + +proc get_config_param {param} { + upvar device device + upvar mode mode + upvar params params + + set spi_params {DATA_WIDTH ASYNC_SPI_CLK NUM_CS NUM_SDI SDI_DELAY} + set index [lsearch $spi_params $param] + + return [lindex $params($device,$mode) $index] +} diff --git a/projects/ad469x_fmc/zed/Makefile b/projects/ad469x_fmc/zed/Makefile new file mode 100644 index 000000000..374a221f4 --- /dev/null +++ b/projects/ad469x_fmc/zed/Makefile @@ -0,0 +1,29 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad469x_fmc_zed + +M_DEPS += ../common/ad469x_bd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v +M_DEPS += ../../../library/util_cdc/sync_bits.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer +LIB_DEPS += axi_pulse_gen + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad469x_fmc/zed/system_bd.tcl b/projects/ad469x_fmc/zed/system_bd.tcl new file mode 100644 index 000000000..7ae0ad128 --- /dev/null +++ b/projects/ad469x_fmc/zed/system_bd.tcl @@ -0,0 +1,25 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + +# specify the spi reference clock frequency in MHz +set spi_clk_ref_frequency 160 + +# specify ADC resolution -- supported resolutions 16 bits +set adc_resolution 16 + +# specify ADC sampling rate in samples/seconds +set adc_sampling_rate 1000000 + +adi_project_files ad469x_fmc_zed [list \ + "../../../library/common/ad_edge_detect.v" \ + "../../../library/util_cdc/sync_bits.v" \ +] + +source ../common/ad469x_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad469x_fmc/zed/system_constr.xdc b/projects/ad469x_fmc/zed/system_constr.xdc new file mode 100644 index 000000000..27989ede7 --- /dev/null +++ b/projects/ad469x_fmc/zed/system_constr.xdc @@ -0,0 +1,11 @@ + +# ad4696_fmc SPI interface + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk] ; ## D09 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs] ; ## G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv] ; ## G07 FMC_LPC_LA00_CC_N + +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0] ; ## H08 FMC_LPC_LA02_N diff --git a/projects/ad469x_fmc/zed/system_project.tcl b/projects/ad469x_fmc/zed/system_project.tcl new file mode 100644 index 000000000..887e0fcf3 --- /dev/null +++ b/projects/ad469x_fmc/zed/system_project.tcl @@ -0,0 +1,24 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_xilinx.tcl +source ../../scripts/adi_board.tcl +source ../common/config.tcl + +adi_project ad469x_fmc_zed 0 [list \ + DATA_WIDTH [get_config_param DATA_WIDTH] \ + ASYNC_SPI_CLK [get_config_param ASYNC_SPI_CLK] \ + NUM_CS [get_config_param NUM_CS] \ + NUM_SDI [get_config_param NUM_SDI] \ + SDI_DELAY [get_config_param SDI_DELAY] \ +] + +adi_project_files ad469x_fmc_zed [list \ + "../../../library/xilinx/common/ad_iobuf.v" \ + "../../../library/common/ad_edge_detect.v" \ + "../../../library/util_cdc/sync_bits.v" \ + "../../common/zed/zed_system_constr.xdc" \ + "system_top.v" \ + "system_constr.xdc" \ + ] + +adi_project_run ad469x_fmc_zed diff --git a/projects/ad469x_fmc/zed/system_top.v b/projects/ad469x_fmc/zed/system_top.v new file mode 100644 index 000000000..3bbd6178c --- /dev/null +++ b/projects/ad469x_fmc/zed/system_top.v @@ -0,0 +1,219 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // ad469x SPI configuration interface + + input ad469x_spi_sdi, + output ad469x_spi_sdo, + output ad469x_spi_sclk, + output ad469x_spi_cs, + output ad469x_spi_cnv, + + input ad469x_busy_alt_gp0, + inout ad469x_resetn); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // instantiations + + assign gpio_i[63:34] = 31'b0; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_ad469x_iobuf ( + .dio_t(gpio_t[32]), + .dio_i(gpio_o[32]), + .dio_o(gpio_i[32]), + .dio_p(ad469x_resetn)); + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .ad469x_spi_sdo (ad469x_spi_sdo), + .ad469x_spi_sdo_t (), + .ad469x_spi_sdi (ad469x_spi_sdi), + .ad469x_spi_cs (ad469x_spi_cs), + .ad469x_spi_sclk (ad469x_spi_sclk), + .ad469x_spi_busy(ad469x_busy_alt_gp0), + .ad469x_spi_cnv(ad469x_spi_cnv), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// ***************************************************************************