scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.
Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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kylex
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f81532d1d7
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365933542d
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@ -22,6 +22,8 @@ set xcvr_tx_index 0
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set xcvr_rx_index 0
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set xcvr_instance NONE
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set use_smartconnect 1
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## Add an instance of an IP to the block design.
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#
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# \param[i_ip] - name of the IP
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@ -703,13 +705,19 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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global sys_hp3_interconnect_index
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global sys_mem_interconnect_index
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global sys_mem_clk_index
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global use_smartconnect
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set p_name_int $p_name
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set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
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set connect_type "smartconnect"
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if {$use_smartconnect == 0} {
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set connect_type "axi_interconnect"
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}
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if {$p_sel eq "SIM"} {
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if {$sys_mem_interconnect_index < 0} {
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ad_ip_instance smartconnect axi_mem_interconnect
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ad_ip_instance $connect_type axi_mem_interconnect
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}
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set m_interconnect_index $sys_mem_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
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@ -718,7 +726,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$p_sel eq "MEM"} {
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if {$sys_mem_interconnect_index < 0} {
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ad_ip_instance smartconnect axi_mem_interconnect
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ad_ip_instance $connect_type axi_mem_interconnect
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}
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set m_interconnect_index $sys_mem_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
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@ -729,7 +737,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp0_interconnect_index < 0} {
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set p_name_int sys_ps7/S_AXI_HP0
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set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
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ad_ip_instance smartconnect axi_hp0_interconnect
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ad_ip_instance $connect_type axi_hp0_interconnect
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}
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set m_interconnect_index $sys_hp0_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
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@ -740,7 +748,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp1_interconnect_index < 0} {
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set p_name_int sys_ps7/S_AXI_HP1
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set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
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ad_ip_instance smartconnect axi_hp1_interconnect
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ad_ip_instance $connect_type axi_hp1_interconnect
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}
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set m_interconnect_index $sys_hp1_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
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@ -751,7 +759,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp2_interconnect_index < 0} {
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set p_name_int sys_ps7/S_AXI_HP2
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set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
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ad_ip_instance smartconnect axi_hp2_interconnect
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ad_ip_instance $connect_type axi_hp2_interconnect
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}
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set m_interconnect_index $sys_hp2_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
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@ -762,7 +770,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp3_interconnect_index < 0} {
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set p_name_int sys_ps7/S_AXI_HP3
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set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
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ad_ip_instance smartconnect axi_hp3_interconnect
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ad_ip_instance $connect_type axi_hp3_interconnect
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}
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set m_interconnect_index $sys_hp3_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
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@ -774,7 +782,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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set p_name_int sys_ps8/S_AXI_HPC0_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP0 {1} [get_bd_cells sys_ps8]
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set_property CONFIG.PSU__AFI0_COHERENCY {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hpc0_interconnect
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ad_ip_instance $connect_type axi_hpc0_interconnect
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}
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set m_interconnect_index $sys_hpc0_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hpc0_interconnect]
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@ -786,7 +794,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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set p_name_int sys_ps8/S_AXI_HPC1_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP1 {1} [get_bd_cells sys_ps8]
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set_property CONFIG.PSU__AFI1_COHERENCY {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hpc1_interconnect
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ad_ip_instance $connect_type axi_hpc1_interconnect
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}
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set m_interconnect_index $sys_hpc1_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hpc1_interconnect]
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@ -797,7 +805,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp0_interconnect_index < 0} {
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set p_name_int sys_ps8/S_AXI_HP0_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hp0_interconnect
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ad_ip_instance $connect_type axi_hp0_interconnect
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}
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set m_interconnect_index $sys_hp0_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
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@ -808,7 +816,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp1_interconnect_index < 0} {
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set p_name_int sys_ps8/S_AXI_HP1_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hp1_interconnect
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ad_ip_instance $connect_type axi_hp1_interconnect
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}
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set m_interconnect_index $sys_hp1_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
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@ -819,7 +827,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp2_interconnect_index < 0} {
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set p_name_int sys_ps8/S_AXI_HP2_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hp2_interconnect
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ad_ip_instance $connect_type axi_hp2_interconnect
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}
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set m_interconnect_index $sys_hp2_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
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@ -830,7 +838,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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if {$sys_hp3_interconnect_index < 0} {
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set p_name_int sys_ps8/S_AXI_HP3_FPD
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set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
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ad_ip_instance smartconnect axi_hp3_interconnect
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ad_ip_instance $connect_type axi_hp3_interconnect
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}
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set m_interconnect_index $sys_hp3_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
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@ -872,20 +880,29 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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ad_connect $p_rst $m_interconnect_cell/ARESETN
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ad_connect $p_clk $m_interconnect_cell/ACLK
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ad_connect $m_interconnect_cell/M00_AXI $p_name_int
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if {$use_smartconnect == 0} {
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ad_connect $p_rst $m_interconnect_cell/M00_ARESETN
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ad_connect $p_clk $m_interconnect_cell/M00_ACLK
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}
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if {$p_intf_clock ne ""} {
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ad_connect $p_clk $p_intf_clock
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}
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} else {
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set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
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set clk_index [lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]]
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if { $clk_index == -1 } {
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incr sys_mem_clk_index
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set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
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ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
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set asocc_clk_pin $m_interconnect_cell/ACLK$sys_mem_clk_index
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if {$use_smartconnect == 1} {
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set clk_index [lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]]
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if { $clk_index == -1 } {
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incr sys_mem_clk_index
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set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
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ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
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set asocc_clk_pin $m_interconnect_cell/ACLK$sys_mem_clk_index
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} else {
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set asocc_clk_pin [lindex [get_bd_pins $m_interconnect_cell/ACLK*] $clk_index]
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}
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} else {
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set asocc_clk_pin [lindex [get_bd_pins $m_interconnect_cell/ACLK*] $clk_index]
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ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN
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ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
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}
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ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
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if {$p_intf_clock ne ""} {
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@ -919,6 +936,10 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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}
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}
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if {($use_smartconnect == 0) && ($m_interconnect_index > 1)} {
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set_property CONFIG.STRATEGY {2} $m_interconnect_cell
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}
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if {$p_sel eq "SIM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HPC0"} {set sys_hpc0_interconnect_index $m_interconnect_index}
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@ -941,21 +962,16 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
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global sys_zynq
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global sys_cpu_interconnect_index
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global use_smartconnect
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set i_str "M$sys_cpu_interconnect_index"
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if {$sys_cpu_interconnect_index < 10} {
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set i_str "M0$sys_cpu_interconnect_index"
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}
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set use_smart_connect 1
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# SmartConnect has higher resource utilization and worse timing closure on older families
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if {$sys_zynq == 1} {
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set use_smart_connect 0
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}
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if {$sys_cpu_interconnect_index == 0} {
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if {$use_smart_connect == 1} {
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if {$use_smartconnect == 1} {
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ad_ip_instance smartconnect axi_cpu_interconnect [ list \
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NUM_MI 1 \
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NUM_SI 1 \
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@ -1091,7 +1107,7 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
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set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
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if {$use_smart_connect == 0} {
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if {$use_smartconnect == 0} {
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ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
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ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
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}
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@ -157,6 +157,7 @@ proc adi_project_create {project_name mode parameter_list device {board "not-app
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global IGNORE_VERSION_CHECK
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global ADI_USE_OOC_SYNTHESIS
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global ADI_USE_INCR_COMP
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global use_smartconnect
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if {![info exists ::env(ADI_PROJECT_DIR)]} {
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set actual_project_name $project_name
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@ -170,6 +171,12 @@ proc adi_project_create {project_name mode parameter_list device {board "not-app
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}
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set p_board $board
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set use_smartconnect 1
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if [regexp "^xc7z" $p_device] {
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# SmartConnect has higher resource utilization and worse timing closure on older families
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set use_smartconnect 0
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}
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if [regexp "^xc7z" $p_device] {
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set sys_zynq 1
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} elseif [regexp "^xck26" $p_device] {
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