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axi_ad9361: Add Altera SERDES interface support

main
AndreiGrozav 2016-10-11 17:16:45 +03:00
parent ae47895666
commit 369dad60b0
3 changed files with 1172 additions and 11 deletions
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583
library/axi_ad9361/altera/axi_ad9361_cmos_if.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_cmos_if (
// physical interface (receive)
rx_clk_in,
rx_frame_in,
rx_data_in,
// physical interface (transmit)
tx_clk_out,
tx_frame_out,
tx_data_out,
// ensm control
enable,
txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in;
input rx_frame_in;
input [11:0] rx_data_in;
// physical interface (transmit)
output tx_clk_out;
output tx_frame_out;
output [11:0] tx_data_out;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input [15:0] up_dac_dld;
input [79:0] up_dac_dwdata;
output [79:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg [ 1:0] rx_frame = 0;
reg [11:0] rx_data_p = 0;
reg rx_error_r1 = 'd0;
reg rx_valid_r1 = 'd0;
reg [23:0] rx_data_r1 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [47:0] rx_data_r2 = 'd0;
reg adc_p_valid = 'd0;
reg [47:0] adc_p_data = 'd0;
reg adc_p_status = 'd0;
reg adc_n_valid = 'd0;
reg [47:0] adc_n_data = 'd0;
reg adc_n_status = 'd0;
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 1:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame_p = 'd0;
reg tx_frame_n = 'd0;
reg [11:0] tx_data_p = 'd0;
reg [11:0] tx_data_n = 'd0;
reg tx_n_frame_p = 'd0;
reg tx_n_frame_n = 'd0;
reg [11:0] tx_n_data_p = 'd0;
reg [11:0] tx_n_data_n = 'd0;
reg tx_p_frame_p = 'd0;
reg tx_p_frame_n = 'd0;
reg [11:0] tx_p_data_p = 'd0;
reg [11:0] tx_p_data_n = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_n_int = 'd0;
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals
wire [ 1:0] rx_frame_s;
wire [ 3:0] rx_frame_4_s;
wire [ 2:0] tx_data_sel_s;
wire [11:0] rx_data_p_s;
wire [11:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s;
genvar l_inst;
// receive data path interface
assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s};
assign rx_frame_4_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_p <= rx_data_p_s;
end
// receive data path for single rf, frame is expected to qualify i only
always @(posedge l_clk) begin
rx_error_r1 <= ~^ rx_frame_s;
rx_valid_r1 <= ^ rx_frame_s;
case (rx_frame_s)
2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
default: rx_data_r1 <= 24'd0;
endcase
end
// receive data path for dual rf, frame is expected to qualify iq for rf-1 only
always @(posedge l_clk) begin
rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
(rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
(rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
case (rx_frame_s)
2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
endcase
case (rx_frame_s)
2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[47:24] <= rx_data_r2[47:24];
endcase
end
// receive data path mux
always @(posedge l_clk) begin
if (adc_r1_mode == 1'b1) begin
adc_p_valid <= rx_valid_r1;
adc_p_data <= {24'd0, rx_data_r1};
adc_p_status <= ~rx_error_r1;
end else begin
adc_p_valid <= rx_valid_r2;
adc_p_data <= rx_data_r2;
adc_p_status <= ~rx_error_r2;
end
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid_int <= adc_n_valid;
adc_data_int <= adc_n_data;
adc_status_int <= adc_n_status;
adc_valid <= adc_valid_int;
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int & locked;
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 2'b10;
end else if (tx_data_cnt[1] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data <= dac_data;
end
case (tx_data_sel_s)
3'b101: begin
tx_frame_p <= 1'b0;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[35:24];
tx_data_n <= tx_data[47:36];
end
3'b100: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b1;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
3'b110: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
default: begin
tx_frame_p <= 1'd0;
tx_frame_n <= 1'd0;
tx_data_p <= 12'd0;
tx_data_n <= 12'd0;
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin
tx_n_frame_p <= tx_frame_p;
tx_n_frame_n <= tx_frame_n;
tx_n_data_p <= tx_data_p;
tx_n_data_n <= tx_data_n;
end
always @(posedge l_clk) begin
tx_p_frame_p <= tx_n_frame_p;
tx_p_frame_n <= tx_n_frame_n;
tx_p_data_p <= tx_n_data_p;
tx_p_data_n <= tx_n_data_n;
end
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
always @(negedge clk) begin
enable_n_int <= enable_int;
txnrx_n_int <= txnrx_int;
end
always @(posedge l_clk) begin
enable_p_int <= enable_n_int;
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in (rx_data_in[l_inst]),
.rx_data_p (rx_data_p_s[l_inst]),
.rx_data_n (rx_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// receive frame interface, ibuf -> idelay -> iddr
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in (rx_frame_in),
.rx_data_p (rx_frame_p_s),
.rx_data_n (rx_frame_n_s),
.up_clk (up_clk),
.up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// transmit data interface, oddr -> obuf
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]),
.tx_data_n (tx_p_data_n[l_inst]),
.tx_data_out (tx_data_out[l_inst]),
.up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// transmit frame interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_p_frame_p),
.tx_data_n (tx_p_frame_n),
.tx_data_out (tx_frame_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[12]),
.up_dwdata (up_dac_dwdata[64:60]),
.up_drdata (up_dac_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// transmit clock interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out (tx_clk_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[13]),
.up_dwdata (up_dac_dwdata[69:65]),
.up_drdata (up_dac_drdata[69:65]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// enable, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out (enable),
.up_clk (up_clk),
.up_dld (up_dac_dld[14]),
.up_dwdata (up_dac_dwdata[74:70]),
.up_drdata (up_dac_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// txnrx, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out (txnrx),
.up_clk (up_clk),
.up_dld (up_dac_dld[15]),
.up_dwdata (up_dac_dwdata[79:75]),
.up_drdata (up_dac_drdata[79:75]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_cmos_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in (rx_clk_in),
.clk (l_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_lvds_if #(
parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
input rst,
input clk,
output l_clk,
// receive data path interface
output reg adc_valid,
output reg [47:0] adc_data,
output reg adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
input mmcm_rst,
input up_clk,
input up_rstn,
input up_enable,
input up_txnrx,
input [ 6:0] up_adc_dld,
input [34:0] up_adc_dwdata,
output [34:0] up_adc_drdata,
input [ 9:0] up_dac_dld,
input [49:0] up_dac_dwdata,
output [49:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// drp interface
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// internal registers
reg [ 3:0] rx_frame = 'd0;
reg rx_error = 'd0;
reg rx_valid = 'd0;
reg [ 5:0] rx_data_3 = 'd0;
reg [ 5:0] rx_data_2 = 'd0;
reg [ 5:0] rx_data_1 = 'd0;
reg [ 5:0] rx_data_0 = 'd0;
reg [23:0] rx_data = 'd0;
reg [ 3:0] tx_frame = 'd0;
reg [ 3:0] tx_p_frame = 'd0;
reg [ 3:0] tx_n_frame = 'd0;
reg [ 5:0] tx_data_d_0 = 'd0;
reg [ 5:0] tx_data_d_1 = 'd0;
reg [ 5:0] tx_data_d_2 = 'd0;
reg [ 5:0] tx_data_d_3 = 'd0;
reg tx_data_sel = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_n_int = 'd0;
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg [47:0] tx_data_lclk = 'd0;
reg [ 5:0] tx_p_data_d_0 = 'd0;
reg [ 5:0] tx_p_data_d_1 = 'd0;
reg [ 5:0] tx_p_data_d_2 = 'd0;
reg [ 5:0] tx_p_data_d_3 = 'd0;
reg [ 5:0] tx_n_data_d_0 = 'd0;
reg [ 5:0] tx_n_data_d_1 = 'd0;
reg [ 5:0] tx_n_data_d_2 = 'd0;
reg [ 5:0] tx_n_data_d_3 = 'd0;
reg adc_n_valid = 'd0;
reg adc_p_valid = 'd0;
reg adc_n_status = 'd0;
reg adc_p_status = 'd0;
reg [47:0] adc_n_data = 'd0;
reg [47:0] adc_p_data = 'd0;
// internal signals
wire s_clk;
wire loaden;
wire [ 7:0] phase_s;
wire [ 3:0] rx_frame_s;
wire [ 5:0] rx_data_s_3;
wire [ 5:0] rx_data_s_2;
wire [ 5:0] rx_data_s_1;
wire [ 5:0] rx_data_s_0;
wire [ 3:0] rx_frame_inv_s;
// unused interface signals
assign up_adc_drdata = 35'b0;
assign up_dac_drdata = 50'b0;
assign delay_locked = 1'b1;
assign rx_frame_inv_s = ~rx_frame;
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_3 <= rx_data_s_3;
rx_data_2 <= rx_data_s_2;
rx_data_1 <= rx_data_s_1;
rx_data_0 <= rx_data_s_0;
if (rx_frame_inv_s == rx_frame_s) begin
rx_error <= 1'b0;
end else begin
rx_error <= 1'b1;
end
case ({adc_r1_mode, rx_frame})
// R2 Mode
5'b01111: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_1, rx_data_3};
rx_data[11: 0] <= {rx_data_0, rx_data_2};
end
5'b01110: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
end
5'b01100: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
end
5'b01000: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
end
5'b00000: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_1, rx_data_3};
rx_data[11: 0] <= {rx_data_0, rx_data_2};
end
5'b00001: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
end
5'b00011: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
end
5'b00111: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
end
// R1 Mode
5'b11100: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_1, rx_data_s_3};
rx_data[11: 0] <= {rx_data_s_0, rx_data_s_2};
end
5'b10110: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
end
5'b11001: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
end
5'b10011: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
end
default: begin
rx_valid <= 1'b0;
rx_data[23:12] <= 12'd0;
rx_data[11: 0] <= 12'd0;
end
endcase
if (rx_valid == 1'b1) begin
adc_p_valid <= 1'b0;
adc_p_data <= {24'd0, rx_data};
end else begin
adc_p_valid <= 1'b1;
adc_p_data <= (adc_r1_mode) ? {24'd0, rx_data} : {rx_data, adc_p_data[23:0]};
end
adc_p_status <= ~rx_error & up_drp_locked;
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid <= adc_n_valid;
adc_data <= adc_n_data;
adc_status <= adc_n_status;
end
always @(posedge clk) begin
if (dac_r1_mode == 1'b0) begin
tx_data_sel <= ~tx_data_sel;
end else begin
tx_data_sel <= 1'b0;
end
case ({dac_r1_mode, tx_data_sel})
2'b10: begin
tx_frame <= 4'b1100;
tx_data_d_0 <= dac_data[11: 6]; // i msb
tx_data_d_1 <= dac_data[23:18]; // q msb
tx_data_d_2 <= dac_data[ 5: 0]; // i lsb
tx_data_d_3 <= dac_data[17:12]; // q lsb
end
2'b00: begin
tx_frame <= 4'b1111;
tx_data_d_0 <= dac_data[11: 6]; // i msb 0
tx_data_d_1 <= dac_data[23:18]; // q msb 0
tx_data_d_2 <= dac_data[ 5: 0]; // i lsb 0
tx_data_d_3 <= dac_data[17:12]; // q lsb 0
end
2'b01: begin
tx_frame <= 4'b0000;
tx_data_d_0 <= dac_data[35:30]; // i msb 1
tx_data_d_1 <= dac_data[47:42]; // q msb 1
tx_data_d_2 <= dac_data[29:24]; // i lsb 1
tx_data_d_3 <= dac_data[41:36]; // q lsb 1
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin
tx_n_frame <= tx_frame;
tx_n_data_d_0 <= tx_data_d_0;
tx_n_data_d_1 <= tx_data_d_1;
tx_n_data_d_2 <= tx_data_d_2;
tx_n_data_d_3 <= tx_data_d_3;
end
always @(posedge l_clk) begin
tx_p_frame <= tx_n_frame;
tx_p_data_d_0 <= tx_n_data_d_0;
tx_p_data_d_1 <= tx_n_data_d_1;
tx_p_data_d_2 <= tx_n_data_d_2;
tx_p_data_d_3 <= tx_n_data_d_3;
end
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
always @(negedge clk) begin
enable_n_int <= enable_int;
txnrx_n_int <= txnrx_int;
end
always @(posedge l_clk) begin
enable_p_int <= enable_n_int;
txnrx_p_int <= txnrx_n_int;
end
// receive data path interface
ad_serdes_in #(
.DATA_WIDTH(6),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
ad_serdes_data_in (
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.locked (up_drp_locked),
.phase (phase_s),
.data_s0 (rx_data_s_0),
.data_s1 (rx_data_s_1),
.data_s2 (rx_data_s_2),
.data_s3 (rx_data_s_3),
.data_s4 (),
.data_s5 (),
.data_s6 (),
.data_s7 (),
.data_in_p (rx_data_in_p),
.data_in_n (rx_data_in_n));
// receive frame interface
ad_serdes_in #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
ad_serdes_frame_in (
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.locked (up_drp_locked),
.phase (phase_s),
.data_s0 (rx_frame_s[0]),
.data_s1 (rx_frame_s[1]),
.data_s2 (rx_frame_s[2]),
.data_s3 (rx_frame_s[3]),
.data_s4 (),
.data_s5 (),
.data_s6 (),
.data_s7 (),
.data_in_p (rx_frame_in_p),
.data_in_n (rx_frame_in_n));
// transmit data interface
ad_serdes_out #(
.DATA_WIDTH(6),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
ad_serdes_data_out (
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (tx_p_data_d_0),
.data_s1 (tx_p_data_d_1),
.data_s2 (tx_p_data_d_2),
.data_s3 (tx_p_data_d_3),
.data_s4 (6'b0),
.data_s5 (6'b0),
.data_s6 (6'b0),
.data_s7 (6'b0),
.data_out_p (tx_data_out_p),
.data_out_n (tx_data_out_n));
// transmit frame interface
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
ad_serdes_frame_out (
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (tx_p_frame[0]),
.data_s1 (tx_p_frame[1]),
.data_s2 (tx_p_frame[2]),
.data_s3 (tx_p_frame[3]),
.data_s4 (1'b1),
.data_s5 (1'b1),
.data_s6 (1'b1),
.data_s7 (1'b1),
.data_out_p (tx_frame_out_p),
.data_out_n (tx_frame_out_n));
// transmit clock interface
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
ad_serdes_tx_clock_out(
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (dac_clksel),
.data_s1 (~dac_clksel),
.data_s2 (dac_clksel),
.data_s3 (~dac_clksel),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_out_p (tx_clk_out_p),
.data_out_n (tx_clk_out_n));
// serdes clock interface
ad_serdes_clk ad_serdes_clk (
.rst (mmcm_rst),
.clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n),
.clk (s_clk),
.div_clk (l_clk),
.out_clk (),
.loaden (loaden),
.phase (phase_s),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
// enable
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
i_enable(
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (enable_p_int),
.data_s1 (enable_p_int),
.data_s2 (enable_p_int),
.data_s3 (enable_p_int),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_out_p (enable),
.data_out_n ());
// txnrx
ad_serdes_out #(
.DATA_WIDTH(1),
.SERDES_FACTOR(4),
.DEVICE_TYPE(DEVICE_TYPE))
i_txnrx(
.rst (mmcm_rst),
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (txnrx_p_int),
.data_s1 (txnrx_p_int),
.data_s2 (txnrx_p_int),
.data_s3 (txnrx_p_int),
.data_s4 (1'b0),
.data_s5 (1'b0),
.data_s6 (1'b0),
.data_s7 (1'b0),
.data_out_p (txnrx),
.data_out_n ());
endmodule
// ***************************************************************************
// ***************************************************************************

33
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -17,6 +17,9 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_lvds_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_clk.v
add_fileset_file ad_serdes_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
add_fileset_file ad_serdes_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
add_fileset_file ad_serdes_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
add_fileset_file ad_lvds_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_in.v
add_fileset_file ad_lvds_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_out.v
add_fileset_file ad_cmos_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
@ -42,8 +45,8 @@ add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/commo
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
add_fileset_file up_tdd_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
add_fileset_file axi_ad9361_lvds_if.v VERILOG PATH axi_ad9361_lvds_if.v
add_fileset_file axi_ad9361_cmos_if.v VERILOG PATH axi_ad9361_cmos_if.v
add_fileset_file axi_ad9361_lvds_if.v VERILOG PATH altera/axi_ad9361_lvds_if.v
add_fileset_file axi_ad9361_cmos_if.v VERILOG PATH altera/axi_ad9361_cmos_if.v
add_fileset_file axi_ad9361_rx_pnmon.v VERILOG PATH axi_ad9361_rx_pnmon.v
add_fileset_file axi_ad9361_rx_channel.v VERILOG PATH axi_ad9361_rx_channel.v
add_fileset_file axi_ad9361_rx.v VERILOG PATH axi_ad9361_rx.v
@ -235,15 +238,23 @@ set_instance_parameter_value alt_ddio_out {SIZE} {1}
set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
add_hdl_instance alt_clk altera_iopll
set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
set_instance_parameter_value alt_clk {gui_use_locked} {1}
set_instance_parameter_value alt_clk {gui_operation_mode} {source synchronous}
set_instance_parameter_value alt_clk {gui_number_of_clocks} {1}
set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
add_hdl_instance alt_serdes_clk_core alt_serdes
set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_in_core alt_serdes
set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_out_core alt_serdes
set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
# updates