Add generic fir filters processes for RF projects
AndreiGrozav
AndreiGrozav
parent
0261eade0c
commit
36a1767329
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_bus_mux #(
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// Channel data width
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parameter DATA_WIDTH = 16) (
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input select_path,
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input valid_in_0,
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input enable_in_0,
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input [DATA_WIDTH-1:0] data_in_0,
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input valid_in_1,
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input enable_in_1,
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input [DATA_WIDTH-1:0] data_in_1,
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output valid_out,
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output enable_out,
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output [DATA_WIDTH-1:0] data_out);
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assign valid_out = (select_path == 0) ? valid_in_0 : valid_in_1;
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assign enable_out = (select_path == 0) ? enable_in_0 : enable_in_1;
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assign data_out = (select_path == 0) ? data_in_0 : data_in_1;
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endmodule
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@ -28,6 +28,7 @@ set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 128
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
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# adrv9009
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@ -28,6 +28,7 @@ set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 128
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
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# ad9371
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###################################################################################################
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###################################################################################################
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##
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# ad_add_decimation_filter - Creates a subsystem based on the Xilinx fir_compiler IP.
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# \param[name] - Subsystem name
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# \param[filter_rate] - Filter rate. E.g., 8
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# \param[n_chan] - Number of channels to filter
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# \param[parallel_paths] - Number of paralell paths. For scenarios where
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# the sampling rate is x times the core clock.
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# \param[core_clk_mhz] - Core clock in MHz
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# \param[sampl_freq_mhz] - Sampling frequency in MHz
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proc ad_add_decimation_filter {name filter_rate n_chan parallel_paths \
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core_clk_mhz sampl_freq_mhz coe_file} {
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global ad_hdl_dir
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create_bd_cell -type hier $name
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set filter_name "fir_decimation"
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create_bd_pin -dir I $name/aclk
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create_bd_pin -dir I $name/active
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# Adding the ad_bus_axis.v file in the project fileset sources_1 will not work
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add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v
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# add filter instances for n channels
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for {set i 0} {$i < $n_chan} {incr i} {
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ad_ip_instance fir_compiler $name/${filter_name}_${i} [ list \
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Decimation_Rate $filter_rate \
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Filter_Type "Decimation" \
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Interpolation_Rate 1 \
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Number_Paths $parallel_paths \
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Clock_Frequency $core_clk_mhz \
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Sample_Frequency $sampl_freq_mhz \
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CoefficientSource COE_File \
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Coefficient_File $coe_file \
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Coefficient_Fractional_Bits 0 \
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Data_Fractional_Bits 15 \
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Coefficient_Sets 1 \
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Coefficient_Sign Signed \
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Coefficient_Structure Inferred \
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Coefficient_Width 16 \
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ColumnConfig 5 \
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Filter_Architecture Systolic_Multiply_Accumulate \
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Number_Channels 1 \
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Output_Rounding_Mode Symmetric_Rounding_to_Zero \
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Output_Width 16 \
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Quantization Integer_Coefficients \
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RateSpecification Frequency_Specification \
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Zero_Pack_Factor 1
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]
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ad_connect $name/aclk $name/${filter_name}_${i}/aclk
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create_bd_pin -dir I $name/valid_in_$i
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create_bd_pin -dir I $name/enable_in_$i
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create_bd_pin -dir O $name/valid_out_$i
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create_bd_pin -dir O $name/enable_out_$i
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create_bd_pin -dir I -from [expr 16*$parallel_paths-1] -to 0 $name/data_in_$i
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create_bd_pin -dir O -from [expr 16*$parallel_paths-1] -to 0 $name/data_out_$i
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create_bd_cell -type module -reference ad_bus_mux $name/out_mux_$i
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set_property -dict [list \
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CONFIG.DATA_WIDTH [expr 16 * $parallel_paths]] [get_bd_cells $name/out_mux_$i]
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ad_connect $name/valid_in_$i $name/out_mux_${i}/valid_in_0
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ad_connect $name/enable_in_$i $name/out_mux_${i}/enable_in_0
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ad_connect $name/data_in_$i $name/out_mux_${i}/data_in_0
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ad_connect $name/valid_in_$i $name/${filter_name}_${i}/s_axis_data_tvalid
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ad_connect $name/enable_in_$i $name/out_mux_${i}/enable_in_1
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ad_connect $name/data_in_$i $name/${filter_name}_${i}/s_axis_data_tdata
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ad_connect $name/${filter_name}_${i}/m_axis_data_tvalid $name/out_mux_${i}/valid_in_1
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ad_connect $name/${filter_name}_${i}/m_axis_data_tdata $name/out_mux_${i}/data_in_1
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ad_connect $name/valid_out_$i $name/out_mux_${i}/valid_out
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ad_connect $name/enable_out_$i $name/out_mux_${i}/enable_out
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ad_connect $name/data_out_$i $name/out_mux_${i}/data_out
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ad_connect $name/out_mux_${i}/select_path $name/active
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}
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}
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###################################################################################################
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###################################################################################################
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##
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# ad_add_interpolation_filter - Creates a subsystem based on the Xilinx fir_compiler IP.
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# \param[name] - Subsystem name
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# \param[filter_rate] - Filter rate. E.g., 8
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# \param[n_chan] - Number of channels to filter
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# \param[parallel_paths] - Number of paralell paths. For scenarios where
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# the sampling rate is x times the core clock.
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# \param[core_clk_mhz] - Core clock in MHz
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# \param[sampl_freq_mhz] - Sampling frequency in MHz
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proc ad_add_interpolation_filter {name filter_rate n_chan parallel_paths \
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core_clk_mhz sampl_freq_mhz coe_file} {
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global ad_hdl_dir
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create_bd_cell -type hier $name
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set filter_name "fir_interpolation"
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add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v
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add_files -norecurse $ad_hdl_dir/library/common/util_pulse_gen.v
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create_bd_pin -dir I $name/aclk
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create_bd_pin -dir I $name/active
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# Create pulse generator for ready/valid signals - This is required because
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# there is only one clock domain for the slave and master data paths.
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# The generator will give a 1 clock cycle pulse every N clock cycle periods.
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# N = data rate.
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create_bd_cell -type module -reference util_pulse_gen $name/rate_gen
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set_property -dict [list \
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CONFIG.PULSE_WIDTH {1} \
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CONFIG.PULSE_PERIOD [expr $filter_rate -1]] [get_bd_cells $name/rate_gen]
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ad_connect $name/aclk $name/rate_gen/clk
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ad_connect $name/rate_gen/pulse_width GND
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ad_connect $name/rate_gen/pulse_period GND
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ad_connect $name/rate_gen/load_config GND
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ad_connect $name/active $name/rate_gen/rstn
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# add filter instances for n channels
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for {set i 0} {$i < $n_chan} {incr i} {
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ad_ip_instance fir_compiler $name/${filter_name}_${i} [ list \
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Decimation_Rate 1 \
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Filter_Type "Interpolation" \
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Interpolation_Rate $filter_rate \
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Number_Paths $parallel_paths \
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Clock_Frequency $core_clk_mhz \
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Sample_Frequency $sampl_freq_mhz \
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CoefficientSource COE_File \
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Coefficient_File $coe_file \
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Coefficient_Fractional_Bits 0 \
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Data_Fractional_Bits 15 \
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Coefficient_Sets 1 \
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Coefficient_Sign Signed \
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Coefficient_Structure Inferred \
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Coefficient_Width 16 \
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ColumnConfig 5 \
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Filter_Architecture Systolic_Multiply_Accumulate \
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Number_Channels 1 \
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Output_Rounding_Mode Symmetric_Rounding_to_Zero \
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Output_Width 16 \
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Quantization Integer_Coefficients \
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RateSpecification Frequency_Specification \
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Zero_Pack_Factor 1
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]
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ad_connect $name/aclk $name/${filter_name}_${i}/aclk
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create_bd_pin -dir I $name/dac_valid_$i
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create_bd_pin -dir I $name/dac_enable_$i
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create_bd_pin -dir O $name/valid_out_$i
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create_bd_pin -dir O $name/enable_out_$i
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create_bd_pin -dir I -from [expr 16*$parallel_paths-1] -to 0 $name/data_in_$i
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create_bd_pin -dir O -from [expr 16*$parallel_paths-1] -to 0 $name/data_out_$i
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ad_ip_instance util_vector_logic $name/logic_and_$i [list \
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C_SIZE 1]
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create_bd_cell -type module -reference ad_bus_mux $name/out_mux_$i
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set_property -dict [list \
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CONFIG.DATA_WIDTH [expr 16 * $parallel_paths]] [get_bd_cells $name/out_mux_$i]
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ad_connect $name/rate_gen/pulse $name/logic_and_$i/Op1
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ad_connect $name/dac_valid_$i $name/logic_and_$i/Op2
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ad_connect $name/logic_and_$i/Res $name/${filter_name}_${i}/s_axis_data_tvalid
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ad_connect $name/${filter_name}_${i}/s_axis_data_tdata $name/data_in_$i
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ad_connect $name/rate_gen/pulse $name/out_mux_${i}/valid_in_1
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ad_connect $name/dac_enable_$i $name/out_mux_${i}/enable_in_1
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ad_connect $name/${filter_name}_${i}/m_axis_data_tdata $name/out_mux_${i}/data_in_1
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ad_connect $name/dac_valid_$i $name/out_mux_${i}/valid_in_0
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ad_connect $name/dac_enable_$i $name/out_mux_${i}/enable_in_0
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ad_connect $name/data_in_$i $name/out_mux_${i}/data_in_0
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ad_connect $name/out_mux_${i}/valid_out $name/valid_out_$i
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ad_connect $name/out_mux_${i}/enable_out $name/enable_out_$i
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ad_connect $name/out_mux_${i}/data_out $name/data_out_$i
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ad_connect $name/active $name/out_mux_${i}/select_path
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}
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}
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@ -335,6 +335,9 @@ proc ad_xcvrpll {m_src m_dst} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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# HP0 high speed interface in case of PSx.
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#
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