util_adxcvr: shared xcvr cores
Rejeesh Kutty
parent
87cf13b0ef
commit
36fbf4fc42
File diff suppressed because it is too large
Load Diff
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@ -1,16 +1,615 @@
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# ip
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## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create util_adxcvr
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adi_ip_files util_adxcvr [list \
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"util_adxcvr_intf.svh" \
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"util_adxcvr_xcm.sv" \
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"util_adxcvr_xch.sv" \
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"util_adxcvr.sv" ]
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"util_adxcvr_xcm.v" \
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"util_adxcvr_xch.v" \
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"util_adxcvr.v" ]
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adi_ip_properties_lite util_adxcvr
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ipx::remove_all_bus_interface [ipx::current_core]
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set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
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for {set n 0} {$n < 16} {incr n} {
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if {($n%4) == 0} {
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adi_if_infer_bus ADI:user:if_xcvr_cm slave up_cm_${n} [list \
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"sel up_cm_sel_${n} "\
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"enb up_cm_enb_${n} "\
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"addr up_cm_addr_${n} "\
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"wr up_cm_wr_${n} "\
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"wdata up_cm_wdata_${n} "\
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"rdata up_cm_rdata_${n} "\
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"ready up_cm_ready_${n} "]
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}
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adi_if_infer_bus ADI:user:if_xcvr_cm slave up_es_${n} [list \
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"sel up_es_sel_${n} "\
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"enb up_es_enb_${n} "\
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"addr up_es_addr_${n} "\
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"wr up_es_wr_${n} "\
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"wdata up_es_wdata_${n} "\
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"rdata up_es_rdata_${n} "\
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"ready up_es_ready_${n} "]
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adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \
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"pll_rst up_rx_pll_rst_${n} "\
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"pll_locked up_rx_pll_locked_${n} "\
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"rst up_rx_rst_${n} "\
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"user_ready up_rx_user_ready_${n} "\
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"rst_done up_rx_rst_done_${n} "\
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"lpm_dfe_n up_rx_lpm_dfe_n_${n} "\
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"rate up_rx_rate_${n} "\
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"sys_clk_sel up_rx_sys_clk_sel_${n} "\
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"out_clk_sel up_rx_out_clk_sel_${n} "\
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"sel up_rx_sel_${n} "\
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"enb up_rx_enb_${n} "\
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"addr up_rx_addr_${n} "\
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"wr up_rx_wr_${n} "\
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"wdata up_rx_wdata_${n} "\
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"rdata up_rx_rdata_${n} "\
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"ready up_rx_ready_${n} "]
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adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \
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"pll_rst up_tx_pll_rst_${n} "\
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"pll_locked up_tx_pll_locked_${n} "\
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"rst up_tx_rst_${n} "\
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"user_ready up_tx_user_ready_${n} "\
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"rst_done up_tx_rst_done_${n} "\
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"lpm_dfe_n up_tx_lpm_dfe_n_${n} "\
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"rate up_tx_rate_${n} "\
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"sys_clk_sel up_tx_sys_clk_sel_${n} "\
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"out_clk_sel up_tx_out_clk_sel_${n} "\
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"sel up_tx_sel_${n} "\
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"enb up_tx_enb_${n} "\
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"addr up_tx_addr_${n} "\
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"wr up_tx_wr_${n} "\
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"wdata up_tx_wdata_${n} "\
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"rdata up_tx_rdata_${n} "\
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"ready up_tx_ready_${n} "]
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ipx::add_bus_interface rx_${n} [ipx::current_core]
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set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
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ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
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ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
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ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
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set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \
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[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
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ipx::add_bus_interface tx_${n} [ipx::current_core]
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set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \
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[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
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set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \
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[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
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set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
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ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
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set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \
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[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
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ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
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set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \
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[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
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}
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
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[ipx::get_ports rx_*0* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
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[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
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[ipx::get_ports tx_*0* -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0))} \
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[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
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[ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \
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[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
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[ipx::get_ports rx_*1* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
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[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
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[ipx::get_ports tx_*1* -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1))} \
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[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
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[ipx::get_ports rx_*2* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
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[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
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[ipx::get_ports tx_*2* -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2))} \
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[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
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[ipx::get_ports rx_*3* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
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[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
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[ipx::get_ports tx_*3* -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3))} \
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[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
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[ipx::get_ports rx_*4* -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
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[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
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[ipx::get_ports tx_*4* -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4))} \
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[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
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[ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency \
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{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
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(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \
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((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
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(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \
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[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]]
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set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
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[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
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|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
||||
[ipx::get_ports rx_*5* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
||||
[ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
||||
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
||||
[ipx::get_ports tx_*5* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5))} \
|
||||
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_ports rx_*6* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
||||
[ipx::get_ports tx_*6* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6))} \
|
||||
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_ports rx_*7* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
||||
[ipx::get_ports tx_*7* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7))} \
|
||||
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_ports rx_*8* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
||||
[ipx::get_ports tx_*8* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8))} \
|
||||
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
|
||||
[ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \
|
||||
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_ports rx_*9* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
||||
[ipx::get_ports tx_*9* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9))} \
|
||||
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_ports rx_*10* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
||||
[ipx::get_ports tx_*10* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10))} \
|
||||
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_ports rx_*11* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
||||
[ipx::get_ports tx_*11* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11))} \
|
||||
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_ports rx_*12* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
||||
[ipx::get_ports tx_*12* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12))} \
|
||||
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
|
||||
[ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \
|
||||
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_ports rx_*13* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
||||
[ipx::get_ports tx_*13* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13))} \
|
||||
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_ports rx_*14* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
||||
[ipx::get_ports tx_*14* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14))} \
|
||||
[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_ports rx_*15* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
||||
[ipx::get_ports tx_*15* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency \
|
||||
{((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15)) or \
|
||||
((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \
|
||||
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15))} \
|
||||
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
|
|
|||
|
|
@ -39,68 +39,85 @@
|
|||
|
||||
module util_adxcvr_xch (
|
||||
|
||||
// rst and clocks
|
||||
// pll interface
|
||||
|
||||
input ref_clk,
|
||||
input pll_rst,
|
||||
|
||||
input qpll_clk,
|
||||
input qpll_ref_clk,
|
||||
input qpll_locked,
|
||||
input qpll2ch_clk,
|
||||
input qpll2ch_ref_clk,
|
||||
input qpll2ch_locked,
|
||||
input cpll_ref_clk,
|
||||
|
||||
// receive
|
||||
|
||||
input rx_p,
|
||||
input rx_n,
|
||||
|
||||
input rx_rst,
|
||||
input rx_clk,
|
||||
input rx_lpm_dfe_n,
|
||||
input [ 2:0] rx_rate,
|
||||
input [ 1:0] rx_sys_clk_sel,
|
||||
input [ 2:0] rx_out_clk_sel,
|
||||
output rx_out_clk,
|
||||
output rx_rst_done,
|
||||
output rx_pll_locked,
|
||||
input rx_user_ready,
|
||||
output [ 3:0] rx_gt_charisk,
|
||||
output [ 3:0] rx_gt_disperr,
|
||||
output [ 3:0] rx_gt_notintable,
|
||||
output [31:0] rx_gt_data,
|
||||
input rx_gt_calign,
|
||||
input rx_clk,
|
||||
output [ 3:0] rx_charisk,
|
||||
output [ 3:0] rx_disperr,
|
||||
output [ 3:0] rx_notintable,
|
||||
output [31:0] rx_data,
|
||||
input rx_calign,
|
||||
|
||||
// transmit
|
||||
|
||||
output tx_p,
|
||||
output tx_n,
|
||||
|
||||
input tx_rst,
|
||||
input tx_clk,
|
||||
input [ 2:0] tx_rate,
|
||||
input [ 1:0] tx_sys_clk_sel,
|
||||
input [ 2:0] tx_out_clk_sel,
|
||||
output tx_out_clk,
|
||||
output tx_rst_done,
|
||||
output tx_pll_locked,
|
||||
input tx_user_ready,
|
||||
input [ 3:0] tx_gt_charisk,
|
||||
input [31:0] tx_gt_data,
|
||||
input tx_clk,
|
||||
input [ 3:0] tx_charisk,
|
||||
input [31:0] tx_data,
|
||||
|
||||
// drp interface
|
||||
// up interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input [ 7:0] up_drp_sel,
|
||||
input up_drp_enb,
|
||||
input [11:0] up_drp_addr,
|
||||
input up_drp_wr,
|
||||
input [15:0] up_drp_wdata,
|
||||
output [15:0] up_drp_rdata,
|
||||
output up_drp_ready);
|
||||
input [ 7:0] up_es_sel,
|
||||
input up_es_enb,
|
||||
input [11:0] up_es_addr,
|
||||
input up_es_wr,
|
||||
input [15:0] up_es_wdata,
|
||||
output [15:0] up_es_rdata,
|
||||
output up_es_ready,
|
||||
input up_rx_pll_rst,
|
||||
output up_rx_pll_locked,
|
||||
input up_rx_rst,
|
||||
input up_rx_user_ready,
|
||||
output up_rx_rst_done,
|
||||
input up_rx_lpm_dfe_n,
|
||||
input [ 2:0] up_rx_rate,
|
||||
input [ 1:0] up_rx_sys_clk_sel,
|
||||
input [ 2:0] up_rx_out_clk_sel,
|
||||
input [ 7:0] up_rx_sel,
|
||||
input up_rx_enb,
|
||||
input [11:0] up_rx_addr,
|
||||
input up_rx_wr,
|
||||
input [15:0] up_rx_wdata,
|
||||
output [15:0] up_rx_rdata,
|
||||
output up_rx_ready,
|
||||
input up_tx_pll_rst,
|
||||
output up_tx_pll_locked,
|
||||
input up_tx_rst,
|
||||
input up_tx_user_ready,
|
||||
output up_tx_rst_done,
|
||||
input up_tx_lpm_dfe_n,
|
||||
input [ 2:0] up_tx_rate,
|
||||
input [ 1:0] up_tx_sys_clk_sel,
|
||||
input [ 2:0] up_tx_out_clk_sel,
|
||||
input [ 7:0] up_tx_sel,
|
||||
input up_tx_enb,
|
||||
input [11:0] up_tx_addr,
|
||||
input up_tx_wr,
|
||||
input [15:0] up_tx_wdata,
|
||||
output [15:0] up_tx_rdata,
|
||||
output up_tx_ready);
|
||||
|
||||
// parameters
|
||||
|
||||
parameter integer XCVR_ID = 0;
|
||||
parameter integer GTH_OR_GTX_N = 0;
|
||||
parameter integer CPLL_TX_OR_RX_N = 0;
|
||||
parameter integer CPLL_FBDIV = 2;
|
||||
parameter integer RX_OUT_DIV = 1;
|
||||
parameter integer RX_CLK25_DIV = 10;
|
||||
|
|
@ -113,60 +130,127 @@ module util_adxcvr_xch (
|
|||
|
||||
// internal registers
|
||||
|
||||
reg up_drp_enb_int = 'd0;
|
||||
reg [11:0] up_drp_addr_int = 'd0;
|
||||
reg up_drp_wr_int = 'd0;
|
||||
reg [15:0] up_drp_wdata_int = 'd0;
|
||||
reg [15:0] up_drp_rdata_int = 'd0;
|
||||
reg up_drp_ready_int = 'd0;
|
||||
reg [15:0] up_es_rdata_int = 'd0;
|
||||
reg up_es_ready_int = 'd0;
|
||||
reg [15:0] up_rx_rdata_int = 'd0;
|
||||
reg up_rx_ready_int = 'd0;
|
||||
reg [15:0] up_tx_rdata_int = 'd0;
|
||||
reg up_tx_ready_int = 'd0;
|
||||
reg [ 2:0] up_sel_int = 'd0;
|
||||
reg up_enb_int = 'd0;
|
||||
reg [11:0] up_addr_int = 'd0;
|
||||
reg up_wr_int = 'd0;
|
||||
reg [15:0] up_wdata_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 3:0] rx_charisk_open_s;
|
||||
wire [ 3:0] rx_disperr_open_s;
|
||||
wire [ 3:0] rx_notintable_open_s;
|
||||
wire [31:0] rx_data_open_s;
|
||||
wire up_cpll_rst;
|
||||
wire up_es_enb_s;
|
||||
wire up_rx_enb_s;
|
||||
wire up_tx_enb_s;
|
||||
wire [15:0] up_rdata_s;
|
||||
wire up_ready_s;
|
||||
wire [ 1:0] rx_sys_clk_sel_s;
|
||||
wire [ 1:0] tx_sys_clk_sel_s;
|
||||
wire [ 1:0] rx_pll_clk_sel_s;
|
||||
wire [ 1:0] tx_pll_clk_sel_s;
|
||||
wire [ 3:0] rx_charisk_open_s;
|
||||
wire [ 3:0] rx_disperr_open_s;
|
||||
wire [ 3:0] rx_notintable_open_s;
|
||||
wire [31:0] rx_data_open_s;
|
||||
wire cpll_locked_s;
|
||||
wire [15:0] up_drp_rdata_s;
|
||||
wire up_drp_ready_s;
|
||||
|
||||
// pll locked
|
||||
// pll
|
||||
|
||||
assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
|
||||
assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s;
|
||||
assign up_cpll_rst = (CPLL_TX_OR_RX_N == 1) ? up_tx_pll_rst : up_rx_pll_rst;
|
||||
assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
|
||||
assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
|
||||
|
||||
// drp access
|
||||
|
||||
assign up_drp_rdata = up_drp_rdata_int;
|
||||
assign up_drp_ready = up_drp_ready_int;
|
||||
assign up_es_rdata = up_es_rdata_int;
|
||||
assign up_es_ready = up_es_ready_int;
|
||||
assign up_rx_rdata = up_rx_rdata_int;
|
||||
assign up_rx_ready = up_rx_ready_int;
|
||||
assign up_tx_rdata = up_tx_rdata_int;
|
||||
assign up_tx_ready = up_tx_ready_int;
|
||||
|
||||
always @(posedge up_clk or negedge up_rstn) begin
|
||||
assign up_es_enb_s = ((up_es_sel == XCVR_ID) ||
|
||||
(up_es_sel == 8'hff)) ? up_es_enb : 1'b0;
|
||||
|
||||
assign up_rx_enb_s = ((up_rx_sel == XCVR_ID) ||
|
||||
(up_rx_sel == 8'hff)) ? up_rx_enb : 1'b0;
|
||||
|
||||
assign up_tx_enb_s = ((up_tx_sel == XCVR_ID) ||
|
||||
(up_tx_sel == 8'hff)) ? up_tx_enb : 1'b0;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_drp_enb_int <= 1'd0;
|
||||
up_drp_addr_int <= 12'd0;
|
||||
up_drp_wr_int <= 1'd0;
|
||||
up_drp_wdata_int <= 15'd0;
|
||||
up_drp_rdata_int <= 15'd0;
|
||||
up_drp_ready_int <= 1'd0;
|
||||
up_es_rdata_int <= 15'd0;
|
||||
up_es_ready_int <= 1'd0;
|
||||
up_rx_rdata_int <= 15'd0;
|
||||
up_rx_ready_int <= 1'd0;
|
||||
up_tx_rdata_int <= 15'd0;
|
||||
up_tx_ready_int <= 1'd0;
|
||||
up_sel_int <= 3'd0;
|
||||
up_enb_int <= 1'd0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 15'd0;
|
||||
end else begin
|
||||
if ((up_drp_sel == XCVR_ID) || (up_drp_sel == 8'hff)) begin
|
||||
up_drp_enb_int <= up_drp_enb;
|
||||
up_drp_addr_int <= up_drp_addr;
|
||||
up_drp_wr_int <= up_drp_wr;
|
||||
up_drp_wdata_int <= up_drp_wdata;
|
||||
up_drp_rdata_int <= up_drp_rdata_s;
|
||||
up_drp_ready_int <= up_drp_ready_s;
|
||||
if (up_sel_int == 3'b100) begin
|
||||
up_es_rdata_int <= up_rdata_s;
|
||||
up_es_ready_int <= up_ready_s;
|
||||
end else begin
|
||||
up_drp_enb_int <= 1'd0;
|
||||
up_drp_addr_int <= 12'd0;
|
||||
up_drp_wr_int <= 1'd0;
|
||||
up_drp_wdata_int <= 15'd0;
|
||||
up_drp_rdata_int <= 15'd0;
|
||||
up_drp_ready_int <= 1'd0;
|
||||
up_es_rdata_int <= 15'd0;
|
||||
up_es_ready_int <= 1'd0;
|
||||
end
|
||||
if (up_sel_int == 3'b101) begin
|
||||
up_rx_rdata_int <= up_rdata_s;
|
||||
up_rx_ready_int <= up_ready_s;
|
||||
end else begin
|
||||
up_rx_rdata_int <= 15'd0;
|
||||
up_rx_ready_int <= 1'd0;
|
||||
end
|
||||
if (up_sel_int == 3'b110) begin
|
||||
up_tx_rdata_int <= up_rdata_s;
|
||||
up_tx_ready_int <= up_ready_s;
|
||||
end else begin
|
||||
up_tx_rdata_int <= 15'd0;
|
||||
up_tx_ready_int <= 1'd0;
|
||||
end
|
||||
if (up_sel_int[2] == 1'b1) begin
|
||||
if (up_ready_s == 1'b1) begin
|
||||
up_sel_int <= 3'b000;
|
||||
end
|
||||
up_enb_int <= 1'b0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 15'd0;
|
||||
end else if (up_es_enb_s == 1'b1) begin
|
||||
up_sel_int <= 3'b100;
|
||||
up_enb_int <= 1'b1;
|
||||
up_addr_int <= up_es_addr;
|
||||
up_wr_int <= up_es_wr;
|
||||
up_wdata_int <= up_es_wdata;
|
||||
end else if (up_rx_enb_s == 1'b1) begin
|
||||
up_sel_int <= 3'b101;
|
||||
up_enb_int <= 1'b1;
|
||||
up_addr_int <= up_rx_addr;
|
||||
up_wr_int <= up_rx_wr;
|
||||
up_wdata_int <= up_rx_wdata;
|
||||
end else if (up_tx_enb_s == 1'b1) begin
|
||||
up_sel_int <= 3'b110;
|
||||
up_enb_int <= 1'b1;
|
||||
up_addr_int <= up_tx_addr;
|
||||
up_wr_int <= up_tx_wr;
|
||||
up_wdata_int <= up_tx_wdata;
|
||||
end else begin
|
||||
up_sel_int <= 3'b000;
|
||||
up_enb_int <= 1'b0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 15'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -175,8 +259,8 @@ module util_adxcvr_xch (
|
|||
|
||||
generate
|
||||
if (GTH_OR_GTX_N == 0) begin
|
||||
assign rx_sys_clk_sel_s = rx_sys_clk_sel;
|
||||
assign tx_sys_clk_sel_s = tx_sys_clk_sel;
|
||||
assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
|
||||
assign tx_sys_clk_sel_s = up_tx_sys_clk_sel;
|
||||
assign rx_pll_clk_sel_s = 2'd0;
|
||||
assign tx_pll_clk_sel_s = 2'd0;
|
||||
end
|
||||
|
|
@ -392,7 +476,7 @@ module util_adxcvr_xch (
|
|||
.CPLLPD (1'b0),
|
||||
.CPLLREFCLKLOST (),
|
||||
.CPLLREFCLKSEL (3'b001),
|
||||
.CPLLRESET (pll_rst),
|
||||
.CPLLRESET (up_cpll_rst),
|
||||
.GTRSVD (16'b0000000000000000),
|
||||
.PCSRSVDIN (16'b0000000000000000),
|
||||
.PCSRSVDIN2 (5'b00000),
|
||||
|
|
@ -404,33 +488,33 @@ module util_adxcvr_xch (
|
|||
.GTGREFCLK (1'd0),
|
||||
.GTNORTHREFCLK0 (1'd0),
|
||||
.GTNORTHREFCLK1 (1'd0),
|
||||
.GTREFCLK0 (ref_clk),
|
||||
.GTREFCLK0 (cpll_ref_clk),
|
||||
.GTREFCLK1 (1'd0),
|
||||
.GTSOUTHREFCLK0 (1'd0),
|
||||
.GTSOUTHREFCLK1 (1'd0),
|
||||
.DRPADDR (up_drp_addr_int[8:0]),
|
||||
.DRPADDR (up_addr_int[8:0]),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_drp_wdata_int),
|
||||
.DRPDO (up_drp_rdata_s),
|
||||
.DRPEN (up_drp_enb_int),
|
||||
.DRPRDY (up_drp_ready_s),
|
||||
.DRPWE (up_drp_wr_int),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPRDY (up_ready_s),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTREFCLKMONITOR (),
|
||||
.QPLLCLK (qpll_clk),
|
||||
.QPLLREFCLK (qpll_ref_clk),
|
||||
.QPLLCLK (qpll2ch_clk),
|
||||
.QPLLREFCLK (qpll2ch_ref_clk),
|
||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||
.DMONITOROUT (),
|
||||
.TX8B10BEN (1'd1),
|
||||
.LOOPBACK (3'd0),
|
||||
.PHYSTATUS (),
|
||||
.RXRATE (rx_rate),
|
||||
.RXRATE (up_rx_rate),
|
||||
.RXVALID (),
|
||||
.RXPD (2'b00),
|
||||
.TXPD (2'b00),
|
||||
.SETERRSTATUS (1'd0),
|
||||
.EYESCANRESET (1'd0),
|
||||
.RXUSERRDY (rx_user_ready),
|
||||
.RXUSERRDY (up_rx_user_ready),
|
||||
.EYESCANDATAERROR (),
|
||||
.EYESCANMODE (1'd0),
|
||||
.EYESCANTRIGGER (1'd0),
|
||||
|
|
@ -444,15 +528,15 @@ module util_adxcvr_xch (
|
|||
.RX8B10BEN (1'd1),
|
||||
.RXUSRCLK (rx_clk),
|
||||
.RXUSRCLK2 (rx_clk),
|
||||
.RXDATA ({rx_data_open_s, rx_gt_data}),
|
||||
.RXDATA ({rx_data_open_s, rx_data}),
|
||||
.RXPRBSERR (),
|
||||
.RXPRBSSEL (3'd0),
|
||||
.RXPRBSCNTRESET (1'd0),
|
||||
.RXDFEXYDEN (1'd0),
|
||||
.RXDFEXYDHOLD (1'd0),
|
||||
.RXDFEXYDOVRDEN (1'd0),
|
||||
.RXDISPERR ({rx_disperr_open_s, rx_gt_disperr}),
|
||||
.RXNOTINTABLE ({rx_notintable_open_s, rx_gt_notintable}),
|
||||
.RXDISPERR ({rx_disperr_open_s, rx_disperr}),
|
||||
.RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
|
||||
.GTXRXP (rx_p),
|
||||
.GTXRXN (rx_n),
|
||||
.RXBUFRESET (1'd0),
|
||||
|
|
@ -476,8 +560,8 @@ module util_adxcvr_xch (
|
|||
.RXBYTEREALIGN (),
|
||||
.RXCOMMADET (),
|
||||
.RXCOMMADETEN (1'd1),
|
||||
.RXMCOMMAALIGNEN (rx_gt_calign),
|
||||
.RXPCOMMAALIGNEN (rx_gt_calign),
|
||||
.RXMCOMMAALIGNEN (rx_calign),
|
||||
.RXPCOMMAALIGNEN (rx_calign),
|
||||
.RXCHANBONDSEQ (),
|
||||
.RXCHBONDEN (1'd0),
|
||||
.RXCHBONDLEVEL (3'd0),
|
||||
|
|
@ -517,17 +601,17 @@ module util_adxcvr_xch (
|
|||
.RXOUTCLK (rx_out_clk),
|
||||
.RXOUTCLKFABRIC (),
|
||||
.RXOUTCLKPCS (),
|
||||
.RXOUTCLKSEL (rx_out_clk_sel),
|
||||
.RXOUTCLKSEL (up_rx_out_clk_sel),
|
||||
.RXDATAVALID (),
|
||||
.RXHEADER (),
|
||||
.RXHEADERVALID (),
|
||||
.RXSTARTOFSEQ (),
|
||||
.RXGEARBOXSLIP (1'd0),
|
||||
.GTRXRESET (rx_rst),
|
||||
.GTRXRESET (up_rx_rst),
|
||||
.RXOOBRESET (1'd0),
|
||||
.RXPCSRESET (1'd0),
|
||||
.RXPMARESET (1'd0),
|
||||
.RXLPMEN (rx_lpm_dfe_n),
|
||||
.RXLPMEN (up_rx_lpm_dfe_n),
|
||||
.RXCOMSASDET (),
|
||||
.RXCOMWAKEDET (),
|
||||
.RXCOMINITDET (),
|
||||
|
|
@ -536,9 +620,9 @@ module util_adxcvr_xch (
|
|||
.RXPOLARITY (1'd0),
|
||||
.RXSLIDE (1'd0),
|
||||
.RXCHARISCOMMA (),
|
||||
.RXCHARISK ({rx_charisk_open_s, rx_gt_charisk}),
|
||||
.RXCHARISK ({rx_charisk_open_s, rx_charisk}),
|
||||
.RXCHBONDI (5'd0),
|
||||
.RXRESETDONE (rx_rst_done),
|
||||
.RXRESETDONE (up_rx_rst_done),
|
||||
.RXQPIEN (1'd0),
|
||||
.RXQPISENN (),
|
||||
.RXQPISENP (),
|
||||
|
|
@ -551,9 +635,9 @@ module util_adxcvr_xch (
|
|||
.TXQPISTRONGPDOWN (1'd0),
|
||||
.TXQPIWEAKPUP (1'd0),
|
||||
.CFGRESET (1'd0),
|
||||
.GTTXRESET (tx_rst),
|
||||
.GTTXRESET (up_tx_rst),
|
||||
.PCSRSVDOUT (),
|
||||
.TXUSERRDY (tx_user_ready),
|
||||
.TXUSERRDY (up_tx_user_ready),
|
||||
.GTRESETSEL (1'd0),
|
||||
.RESETOVRD (1'd0),
|
||||
.TXCHARDISPMODE (8'd0),
|
||||
|
|
@ -562,7 +646,7 @@ module util_adxcvr_xch (
|
|||
.TXUSRCLK2 (tx_clk),
|
||||
.TXELECIDLE (1'd0),
|
||||
.TXMARGIN (3'd0),
|
||||
.TXRATE (tx_rate),
|
||||
.TXRATE (up_tx_rate),
|
||||
.TXSWING (1'd0),
|
||||
.TXPRBSFORCEERR (1'd0),
|
||||
.TXDLYBYPASS (1'd1),
|
||||
|
|
@ -588,22 +672,22 @@ module util_adxcvr_xch (
|
|||
.TXINHIBIT (1'd0),
|
||||
.TXMAINCURSOR (7'b0000000),
|
||||
.TXPISOPD (1'd0),
|
||||
.TXDATA ({32'd0, tx_gt_data}),
|
||||
.TXDATA ({32'd0, tx_data}),
|
||||
.GTXTXP (tx_p),
|
||||
.GTXTXN (tx_n),
|
||||
.TXOUTCLK (tx_out_clk),
|
||||
.TXOUTCLKFABRIC (),
|
||||
.TXOUTCLKPCS (),
|
||||
.TXOUTCLKSEL (tx_out_clk_sel),
|
||||
.TXOUTCLKSEL (up_tx_out_clk_sel),
|
||||
.TXRATEDONE (),
|
||||
.TXCHARISK ({4'd0, tx_gt_charisk}),
|
||||
.TXCHARISK ({4'd0, tx_charisk}),
|
||||
.TXGEARBOXREADY (),
|
||||
.TXHEADER (3'd0),
|
||||
.TXSEQUENCE (7'd0),
|
||||
.TXSTARTSEQ (1'd0),
|
||||
.TXPCSRESET (1'd0),
|
||||
.TXPMARESET (1'd0),
|
||||
.TXRESETDONE (tx_rst_done),
|
||||
.TXRESETDONE (up_tx_rst_done),
|
||||
.TXCOMFINISH (),
|
||||
.TXCOMINIT (1'd0),
|
||||
.TXCOMSAS (1'd0),
|
||||
|
|
@ -620,10 +704,10 @@ module util_adxcvr_xch (
|
|||
|
||||
generate
|
||||
if (GTH_OR_GTX_N == 1) begin
|
||||
assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
|
||||
assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
|
||||
assign rx_pll_clk_sel_s = rx_sys_clk_sel;
|
||||
assign tx_pll_clk_sel_s = tx_sys_clk_sel;
|
||||
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
|
||||
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
|
||||
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
|
||||
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -1025,14 +1109,14 @@ module util_adxcvr_xch (
|
|||
.CPLLLOCKEN (1'd1),
|
||||
.CPLLPD (1'b0),
|
||||
.CPLLREFCLKSEL (3'b001),
|
||||
.CPLLRESET (pll_rst),
|
||||
.CPLLRESET (up_cpll_rst),
|
||||
.DMONFIFORESET (1'd0),
|
||||
.DMONITORCLK (1'd0),
|
||||
.DRPADDR (up_drp_addr_int[8:0]),
|
||||
.DRPADDR (up_addr_int[8:0]),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_drp_wdata_int),
|
||||
.DRPEN (up_drp_enb_int),
|
||||
.DRPWE (up_drp_wr_int),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPWE (up_wr_int),
|
||||
.EVODDPHICALDONE (1'd0),
|
||||
.EVODDPHICALSTART (1'd0),
|
||||
.EVODDPHIDRDEN (1'd0),
|
||||
|
|
@ -1047,14 +1131,14 @@ module util_adxcvr_xch (
|
|||
.GTHRXP (rx_p),
|
||||
.GTNORTHREFCLK0 (1'd0),
|
||||
.GTNORTHREFCLK1 (1'd0),
|
||||
.GTREFCLK0 (ref_clk),
|
||||
.GTREFCLK0 (cpll_ref_clk),
|
||||
.GTREFCLK1 (1'd0),
|
||||
.GTRESETSEL (1'd0),
|
||||
.GTRSVD (15'd0),
|
||||
.GTRXRESET (rx_rst),
|
||||
.GTRXRESET (up_rx_rst),
|
||||
.GTSOUTHREFCLK0 (1'd0),
|
||||
.GTSOUTHREFCLK1 (1'd0),
|
||||
.GTTXRESET (tx_rst),
|
||||
.GTTXRESET (up_tx_rst),
|
||||
.LOOPBACK (3'd0),
|
||||
.LPBKRXTXSEREN (1'd0),
|
||||
.LPBKTXRXSEREN (1'd0),
|
||||
|
|
@ -1065,8 +1149,8 @@ module util_adxcvr_xch (
|
|||
.PCSRSVDIN (16'd0),
|
||||
.PCSRSVDIN2 (5'd0),
|
||||
.PMARSVDIN (5'd0),
|
||||
.QPLL0CLK (qpll_clk),
|
||||
.QPLL0REFCLK (qpll_ref_clk),
|
||||
.QPLL0CLK (qpll2ch_clk),
|
||||
.QPLL0REFCLK (qpll2ch_ref_clk),
|
||||
.QPLL1CLK (1'd0),
|
||||
.QPLL1REFCLK (1'd0),
|
||||
.RESETOVRD (1'd0),
|
||||
|
|
@ -1130,7 +1214,7 @@ module util_adxcvr_xch (
|
|||
.RXELECIDLEMODE (2'b11),
|
||||
.RXGEARBOXSLIP (1'd0),
|
||||
.RXLATCLK (1'd0),
|
||||
.RXLPMEN (rx_lpm_dfe_n),
|
||||
.RXLPMEN (up_rx_lpm_dfe_n),
|
||||
.RXLPMGCHOLD (1'd0),
|
||||
.RXLPMGCOVRDEN (1'd0),
|
||||
.RXLPMHFHOLD (1'd0),
|
||||
|
|
@ -1139,7 +1223,7 @@ module util_adxcvr_xch (
|
|||
.RXLPMLFKLOVRDEN (1'd0),
|
||||
.RXLPMOSHOLD (1'd0),
|
||||
.RXLPMOSOVRDEN (1'd0),
|
||||
.RXMCOMMAALIGNEN (rx_gt_calign),
|
||||
.RXMCOMMAALIGNEN (rx_calign),
|
||||
.RXMONITORSEL (2'd0),
|
||||
.RXOOBRESET (1'd0),
|
||||
.RXOSCALRESET (1'd0),
|
||||
|
|
@ -1151,8 +1235,8 @@ module util_adxcvr_xch (
|
|||
.RXOSINTSTROBE (1'd0),
|
||||
.RXOSINTTESTOVRDEN (1'd0),
|
||||
.RXOSOVRDEN (1'd0),
|
||||
.RXOUTCLKSEL (rx_out_clk_sel),
|
||||
.RXPCOMMAALIGNEN (rx_gt_calign),
|
||||
.RXOUTCLKSEL (up_rx_out_clk_sel),
|
||||
.RXPCOMMAALIGNEN (rx_calign),
|
||||
.RXPCSRESET (1'd0),
|
||||
.RXPD (2'd0),
|
||||
.RXPHALIGN (1'd0),
|
||||
|
|
@ -1167,7 +1251,7 @@ module util_adxcvr_xch (
|
|||
.RXPRBSSEL (4'd0),
|
||||
.RXPROGDIVRESET (1'd0),
|
||||
.RXQPIEN (1'd0),
|
||||
.RXRATE (rx_rate),
|
||||
.RXRATE (up_rx_rate),
|
||||
.RXRATEMODE (1'd0),
|
||||
.RXSLIDE (1'd0),
|
||||
.RXSLIPOUTCLK (1'd0),
|
||||
|
|
@ -1176,7 +1260,7 @@ module util_adxcvr_xch (
|
|||
.RXSYNCIN (1'd0),
|
||||
.RXSYNCMODE (1'd0),
|
||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||
.RXUSERRDY (rx_user_ready),
|
||||
.RXUSERRDY (up_rx_user_ready),
|
||||
.RXUSRCLK (rx_clk),
|
||||
.RXUSRCLK2 (rx_clk),
|
||||
.RX8B10BEN (1'd1),
|
||||
|
|
@ -1188,8 +1272,8 @@ module util_adxcvr_xch (
|
|||
.TXCOMWAKE (1'd0),
|
||||
.TXCTRL0 (16'd0),
|
||||
.TXCTRL1 (16'd0),
|
||||
.TXCTRL2 ({4'd0, tx_gt_charisk}),
|
||||
.TXDATA ({32'd0, tx_gt_data}),
|
||||
.TXCTRL2 ({4'd0, tx_charisk}),
|
||||
.TXDATA ({32'd0, tx_data}),
|
||||
.TXDATAEXTENDRSVD (8'd0),
|
||||
.TXDEEMPH (1'd0),
|
||||
.TXDETECTRX (1'd0),
|
||||
|
|
@ -1207,7 +1291,7 @@ module util_adxcvr_xch (
|
|||
.TXLATCLK (1'd0),
|
||||
.TXMAINCURSOR (7'b1000000),
|
||||
.TXMARGIN (3'd0),
|
||||
.TXOUTCLKSEL (tx_out_clk_sel),
|
||||
.TXOUTCLKSEL (up_tx_out_clk_sel),
|
||||
.TXPCSRESET (1'd0),
|
||||
.TXPD (2'd0),
|
||||
.TXPDELECIDLEMODE (1'd0),
|
||||
|
|
@ -1233,11 +1317,11 @@ module util_adxcvr_xch (
|
|||
.TXPRBSSEL (4'd0),
|
||||
.TXPRECURSOR (5'd0),
|
||||
.TXPRECURSORINV (1'd0),
|
||||
.TXPROGDIVRESET (tx_rst),
|
||||
.TXPROGDIVRESET (up_tx_rst),
|
||||
.TXQPIBIASEN (1'd0),
|
||||
.TXQPISTRONGPDOWN (1'd0),
|
||||
.TXQPIWEAKPUP (1'd0),
|
||||
.TXRATE (tx_rate),
|
||||
.TXRATE (up_tx_rate),
|
||||
.TXRATEMODE (1'd0),
|
||||
.TXSEQUENCE (7'd0),
|
||||
.TXSWING (1'd0),
|
||||
|
|
@ -1245,7 +1329,7 @@ module util_adxcvr_xch (
|
|||
.TXSYNCIN (1'd0),
|
||||
.TXSYNCMODE (1'd0),
|
||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||
.TXUSERRDY (tx_user_ready),
|
||||
.TXUSERRDY (up_tx_user_ready),
|
||||
.TXUSRCLK (tx_clk),
|
||||
.TXUSRCLK2 (tx_clk),
|
||||
.TX8B10BBYPASS (8'd0),
|
||||
|
|
@ -1259,8 +1343,8 @@ module util_adxcvr_xch (
|
|||
.CPLLLOCK (cpll_locked_s),
|
||||
.CPLLREFCLKLOST (),
|
||||
.DMONITOROUT (),
|
||||
.DRPDO (up_drp_rdata_s),
|
||||
.DRPRDY (up_drp_ready_s),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPRDY (up_ready_s),
|
||||
.EYESCANDATAERROR (),
|
||||
.GTHTXN (tx_n),
|
||||
.GTHTXP (tx_p),
|
||||
|
|
@ -1292,11 +1376,11 @@ module util_adxcvr_xch (
|
|||
.RXCOMMADET (),
|
||||
.RXCOMSASDET (),
|
||||
.RXCOMWAKEDET (),
|
||||
.RXCTRL0 ({rx_charisk_open_s, rx_gt_charisk}),
|
||||
.RXCTRL1 ({rx_disperr_open_s, rx_gt_disperr}),
|
||||
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
|
||||
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
|
||||
.RXCTRL2 (),
|
||||
.RXCTRL3 ({rx_notintable_open_s, rx_gt_notintable}),
|
||||
.RXDATA ({rx_data_open_s, rx_gt_data}),
|
||||
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
|
||||
.RXDATA ({rx_data_open_s, rx_data}),
|
||||
.RXDATAEXTENDRSVD (),
|
||||
.RXDATAVALID (),
|
||||
.RXDLYSRESETDONE (),
|
||||
|
|
@ -1321,7 +1405,7 @@ module util_adxcvr_xch (
|
|||
.RXQPISENP (),
|
||||
.RXRATEDONE (),
|
||||
.RXRECCLKOUT (),
|
||||
.RXRESETDONE (rx_rst_done),
|
||||
.RXRESETDONE (up_rx_rst_done),
|
||||
.RXSLIDERDY (),
|
||||
.RXSLIPDONE (),
|
||||
.RXSLIPOUTCLKRDY (),
|
||||
|
|
@ -1344,7 +1428,7 @@ module util_adxcvr_xch (
|
|||
.TXQPISENN (),
|
||||
.TXQPISENP (),
|
||||
.TXRATEDONE (),
|
||||
.TXRESETDONE (tx_rst_done),
|
||||
.TXRESETDONE (up_tx_rst_done),
|
||||
.TXSYNCDONE (),
|
||||
.TXSYNCOUT ());
|
||||
end
|
||||
|
|
|
|||
|
|
@ -41,45 +41,83 @@ module util_adxcvr_xcm (
|
|||
|
||||
// reset and clocks
|
||||
|
||||
input ref_clk,
|
||||
input pll_rst,
|
||||
output qpll_clk,
|
||||
output qpll_ref_clk,
|
||||
output qpll_locked,
|
||||
|
||||
input qpll_ref_clk,
|
||||
output qpll2ch_clk,
|
||||
output qpll2ch_ref_clk,
|
||||
output qpll2ch_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_drp_sel,
|
||||
input [11:0] up_drp_addr,
|
||||
input up_drp_wr,
|
||||
input [15:0] up_drp_wdata,
|
||||
output [15:0] up_drp_rdata,
|
||||
output up_drp_ready);
|
||||
input up_qpll_rst,
|
||||
input [ 7:0] up_cm_sel,
|
||||
input up_cm_enb,
|
||||
input [11:0] up_cm_addr,
|
||||
input up_cm_wr,
|
||||
input [15:0] up_cm_wdata,
|
||||
output [15:0] up_cm_rdata,
|
||||
output up_cm_ready);
|
||||
|
||||
// parameters
|
||||
|
||||
parameter integer XCVR_ID = 0;
|
||||
parameter integer GTH_OR_GTX_N = 0;
|
||||
parameter integer QPLL_ENABLE = 1;
|
||||
parameter integer QPLL_REFCLK_DIV = 2;
|
||||
parameter integer QPLL_FBDIV_RATIO = 1;
|
||||
parameter [26:0] QPLL_CFG = 27'h06801C1;
|
||||
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_enb_int = 'd0;
|
||||
reg [11:0] up_addr_int = 'd0;
|
||||
reg up_wr_int = 'd0;
|
||||
reg [15:0] up_wdata_int = 'd0;
|
||||
reg [15:0] up_rdata_int = 'd0;
|
||||
reg up_ready_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] up_rdata_s;
|
||||
wire up_ready_s;
|
||||
|
||||
// drp access
|
||||
|
||||
assign up_cm_rdata = up_rdata_int;
|
||||
assign up_cm_ready = up_ready_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_enb_int <= 1'd0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 16'd0;
|
||||
up_rdata_int <= 16'd0;
|
||||
up_ready_int <= 1'd0;
|
||||
end else begin
|
||||
if ((up_cm_sel == XCVR_ID) || (up_cm_sel == 8'hff)) begin
|
||||
up_enb_int <= up_cm_enb;
|
||||
up_addr_int <= up_cm_addr;
|
||||
up_wr_int <= up_cm_wr;
|
||||
up_wdata_int <= up_cm_wdata;
|
||||
up_rdata_int <= up_rdata_s;
|
||||
up_ready_int <= up_ready_s;
|
||||
end else begin
|
||||
up_enb_int <= 1'd0;
|
||||
up_addr_int <= 12'd0;
|
||||
up_wr_int <= 1'd0;
|
||||
up_wdata_int <= 16'd0;
|
||||
up_rdata_int <= 16'd0;
|
||||
up_ready_int <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
generate
|
||||
if (QPLL_ENABLE == 0) begin
|
||||
assign qpll_clk = 1'd0;
|
||||
assign qpll_ref_clk = 1'd0;
|
||||
assign qpll_locked = 1'd0;
|
||||
assign up_drp_rdata = 16'd0;
|
||||
assign up_drp_ready = 1'd0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
|
||||
if (GTH_OR_GTX_N == 0) begin
|
||||
GTXE2_COMMON #(
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_QPLLREFCLK_SEL (3'b001),
|
||||
|
|
@ -102,32 +140,32 @@ module util_adxcvr_xcm (
|
|||
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
|
||||
i_gtxe2_common (
|
||||
.DRPCLK (up_clk),
|
||||
.DRPEN (up_drp_sel),
|
||||
.DRPADDR (up_drp_addr[7:0]),
|
||||
.DRPWE (up_drp_wr),
|
||||
.DRPDI (up_drp_wdata),
|
||||
.DRPDO (up_drp_rdata),
|
||||
.DRPRDY (up_drp_ready),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPADDR (up_addr_int[7:0]),
|
||||
.DRPWE (up_wr_int),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPRDY (up_ready_s),
|
||||
.GTGREFCLK (1'd0),
|
||||
.GTNORTHREFCLK0 (1'd0),
|
||||
.GTNORTHREFCLK1 (1'd0),
|
||||
.GTREFCLK0 (ref_clk),
|
||||
.GTREFCLK0 (qpll_ref_clk),
|
||||
.GTREFCLK1 (1'd0),
|
||||
.GTSOUTHREFCLK0 (1'd0),
|
||||
.GTSOUTHREFCLK1 (1'd0),
|
||||
.QPLLDMONITOR (),
|
||||
.QPLLOUTCLK (qpll_clk),
|
||||
.QPLLOUTREFCLK (qpll_ref_clk),
|
||||
.QPLLOUTCLK (qpll2ch_clk),
|
||||
.QPLLOUTREFCLK (qpll2ch_ref_clk),
|
||||
.REFCLKOUTMONITOR (),
|
||||
.QPLLFBCLKLOST (),
|
||||
.QPLLLOCK (qpll_locked),
|
||||
.QPLLLOCK (qpll2ch_locked),
|
||||
.QPLLLOCKDETCLK (up_clk),
|
||||
.QPLLLOCKEN (1'd1),
|
||||
.QPLLOUTRESET (1'd0),
|
||||
.QPLLPD (1'd0),
|
||||
.QPLLREFCLKLOST (),
|
||||
.QPLLREFCLKSEL (3'b001),
|
||||
.QPLLRESET (pll_rst),
|
||||
.QPLLRESET (up_qpll_rst),
|
||||
.QPLLRSVD1 (16'b0000000000000000),
|
||||
.QPLLRSVD2 (5'b11111),
|
||||
.BGBYPASSB (1'd1),
|
||||
|
|
@ -140,7 +178,7 @@ module util_adxcvr_xcm (
|
|||
endgenerate
|
||||
|
||||
generate
|
||||
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
|
||||
if (GTH_OR_GTX_N == 1) begin
|
||||
GTHE3_COMMON #(
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_VERSION (2),
|
||||
|
|
@ -221,18 +259,18 @@ module util_adxcvr_xcm (
|
|||
.BGPDB (1'd1),
|
||||
.BGRCALOVRD (5'b11111),
|
||||
.BGRCALOVRDENB (1'd1),
|
||||
.DRPADDR (up_drp_addr[8:0]),
|
||||
.DRPADDR (up_addr_int[8:0]),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_drp_wdata),
|
||||
.DRPEN (up_drp_sel),
|
||||
.DRPWE (up_drp_wr),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK0 (1'd0),
|
||||
.GTGREFCLK1 (1'd0),
|
||||
.GTNORTHREFCLK00 (1'd0),
|
||||
.GTNORTHREFCLK01 (1'd0),
|
||||
.GTNORTHREFCLK10 (1'd0),
|
||||
.GTNORTHREFCLK11 (1'd0),
|
||||
.GTREFCLK00 (ref_clk),
|
||||
.GTREFCLK00 (qpll_ref_clk),
|
||||
.GTREFCLK01 (1'd0),
|
||||
.GTREFCLK10 (1'd0),
|
||||
.GTREFCLK11 (1'd0),
|
||||
|
|
@ -252,7 +290,7 @@ module util_adxcvr_xcm (
|
|||
.QPLL0LOCKEN (1'd1),
|
||||
.QPLL0PD (1'd0),
|
||||
.QPLL0REFCLKSEL (3'b001),
|
||||
.QPLL0RESET (pll_rst),
|
||||
.QPLL0RESET (up_qpll_rst),
|
||||
.QPLL1CLKRSVD0 (1'd0),
|
||||
.QPLL1CLKRSVD1 (1'd0),
|
||||
.QPLL1LOCKDETCLK (1'd0),
|
||||
|
|
@ -261,16 +299,16 @@ module util_adxcvr_xcm (
|
|||
.QPLL1REFCLKSEL (3'b001),
|
||||
.QPLL1RESET (1'd1),
|
||||
.RCALENB (1'd1),
|
||||
.DRPDO (up_drp_rdata),
|
||||
.DRPRDY (up_drp_ready),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPRDY (up_ready_s),
|
||||
.PMARSVDOUT0 (),
|
||||
.PMARSVDOUT1 (),
|
||||
.QPLLDMONITOR0 (),
|
||||
.QPLLDMONITOR1 (),
|
||||
.QPLL0FBCLKLOST (),
|
||||
.QPLL0LOCK (qpll_locked),
|
||||
.QPLL0OUTCLK (qpll_clk),
|
||||
.QPLL0OUTREFCLK (qpll_ref_clk),
|
||||
.QPLL0LOCK (qpll2ch_locked),
|
||||
.QPLL0OUTCLK (qpll2ch_clk),
|
||||
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
|
||||
.QPLL0REFCLKLOST (),
|
||||
.QPLL1FBCLKLOST (),
|
||||
.QPLL1LOCK (),
|
||||
|
|
|
|||
Loading…
Reference in New Issue