From 36fbf4fc42c5c2c30a6f87d28ba8d9a630f9b320 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 17 Jun 2016 11:59:42 -0400 Subject: [PATCH] util_adxcvr: shared xcvr cores --- library/util_adxcvr/util_adxcvr.v | 2839 +++++++++++++----------- library/util_adxcvr/util_adxcvr_ip.tcl | 609 ++++- library/util_adxcvr/util_adxcvr_xch.v | 366 +-- library/util_adxcvr/util_adxcvr_xcm.v | 132 +- 4 files changed, 2506 insertions(+), 1440 deletions(-) diff --git a/library/util_adxcvr/util_adxcvr.v b/library/util_adxcvr/util_adxcvr.v index c7aa11320..5be095b9b 100644 --- a/library/util_adxcvr/util_adxcvr.v +++ b/library/util_adxcvr/util_adxcvr.v @@ -34,6 +34,7 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** +// AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! `timescale 1ns/1ps @@ -42,619 +43,619 @@ module util_adxcvr ( input up_rstn, input up_clk, - input qpll_ref_clk_00, - input cpll_ref_clk_00, + input qpll_ref_clk_0, + input cpll_ref_clk_0, - input rx_00_p, - input rx_00_n, - output rx_out_clk_00, - input rx_clk_00, - output [ 3:0] rx_charisk_00, - output [ 3:0] rx_disperr_00, - output [ 3:0] rx_notintable_00, - output [31:0] rx_data_00, - input rx_calign_00, + input rx_0_p, + input rx_0_n, + output rx_out_clk_0, + input rx_clk_0, + output [ 3:0] rx_charisk_0, + output [ 3:0] rx_disperr_0, + output [ 3:0] rx_notintable_0, + output [31:0] rx_data_0, + input rx_calign_0, - output tx_00_p, - output tx_00_n, - output tx_out_clk_00, - input tx_clk_00, - input [ 3:0] tx_charisk_00, - input [31:0] tx_data_00, + output tx_0_p, + output tx_0_n, + output tx_out_clk_0, + input tx_clk_0, + input [ 3:0] tx_charisk_0, + input [31:0] tx_data_0, - input [ 7:0] up_cm_sel_00, - input up_cm_enb_00, - input [11:0] up_cm_addr_00, - input up_cm_wr_00, - input [15:0] up_cm_wdata_00, - output [15:0] up_cm_rdata_00, - output up_cm_ready_00, - input [ 7:0] up_es_sel_00, - input up_es_enb_00, - input [11:0] up_es_addr_00, - input up_es_wr_00, - input [15:0] up_es_wdata_00, - output [15:0] up_es_rdata_00, - output up_es_ready_00, - input up_rx_pll_rst_00, - output up_rx_pll_locked_00, - input up_rx_rst_00, - input up_rx_user_ready_00, - output up_rx_rst_done_00, - input up_rx_lpm_dfe_n_00, - input [ 2:0] up_rx_rate_00, - input [ 1:0] up_rx_sys_clk_sel_00, - input [ 2:0] up_rx_out_clk_sel_00, - input [ 7:0] up_rx_sel_00, - input up_rx_enb_00, - input [11:0] up_rx_addr_00, - input up_rx_wr_00, - input [15:0] up_rx_wdata_00, - output [15:0] up_rx_rdata_00, - output up_rx_ready_00, - input up_tx_pll_rst_00, - output up_tx_pll_locked_00, - input up_tx_rst_00, - input up_tx_user_ready_00, - output up_tx_rst_done_00, - input up_tx_lpm_dfe_n_00, - input [ 2:0] up_tx_rate_00, - input [ 1:0] up_tx_sys_clk_sel_00, - input [ 2:0] up_tx_out_clk_sel_00, - input [ 7:0] up_tx_sel_00, - input up_tx_enb_00, - input [11:0] up_tx_addr_00, - input up_tx_wr_00, - input [15:0] up_tx_wdata_00, - output [15:0] up_tx_rdata_00, - output up_tx_ready_00, + input [ 7:0] up_cm_sel_0, + input up_cm_enb_0, + input [11:0] up_cm_addr_0, + input up_cm_wr_0, + input [15:0] up_cm_wdata_0, + output [15:0] up_cm_rdata_0, + output up_cm_ready_0, + input [ 7:0] up_es_sel_0, + input up_es_enb_0, + input [11:0] up_es_addr_0, + input up_es_wr_0, + input [15:0] up_es_wdata_0, + output [15:0] up_es_rdata_0, + output up_es_ready_0, + input up_rx_pll_rst_0, + output up_rx_pll_locked_0, + input up_rx_rst_0, + input up_rx_user_ready_0, + output up_rx_rst_done_0, + input up_rx_lpm_dfe_n_0, + input [ 2:0] up_rx_rate_0, + input [ 1:0] up_rx_sys_clk_sel_0, + input [ 2:0] up_rx_out_clk_sel_0, + input [ 7:0] up_rx_sel_0, + input up_rx_enb_0, + input [11:0] up_rx_addr_0, + input up_rx_wr_0, + input [15:0] up_rx_wdata_0, + output [15:0] up_rx_rdata_0, + output up_rx_ready_0, + input up_tx_pll_rst_0, + output up_tx_pll_locked_0, + input up_tx_rst_0, + input up_tx_user_ready_0, + output up_tx_rst_done_0, + input up_tx_lpm_dfe_n_0, + input [ 2:0] up_tx_rate_0, + input [ 1:0] up_tx_sys_clk_sel_0, + input [ 2:0] up_tx_out_clk_sel_0, + input [ 7:0] up_tx_sel_0, + input up_tx_enb_0, + input [11:0] up_tx_addr_0, + input up_tx_wr_0, + input [15:0] up_tx_wdata_0, + output [15:0] up_tx_rdata_0, + output up_tx_ready_0, - input cpll_ref_clk_01, + input cpll_ref_clk_1, - input rx_01_p, - input rx_01_n, - output rx_out_clk_01, - input rx_clk_01, - output [ 3:0] rx_charisk_01, - output [ 3:0] rx_disperr_01, - output [ 3:0] rx_notintable_01, - output [31:0] rx_data_01, - input rx_calign_01, + input rx_1_p, + input rx_1_n, + output rx_out_clk_1, + input rx_clk_1, + output [ 3:0] rx_charisk_1, + output [ 3:0] rx_disperr_1, + output [ 3:0] rx_notintable_1, + output [31:0] rx_data_1, + input rx_calign_1, - output tx_01_p, - output tx_01_n, - output tx_out_clk_01, - input tx_clk_01, - input [ 3:0] tx_charisk_01, - input [31:0] tx_data_01, + output tx_1_p, + output tx_1_n, + output tx_out_clk_1, + input tx_clk_1, + input [ 3:0] tx_charisk_1, + input [31:0] tx_data_1, - input [ 7:0] up_es_sel_01, - input up_es_enb_01, - input [11:0] up_es_addr_01, - input up_es_wr_01, - input [15:0] up_es_wdata_01, - output [15:0] up_es_rdata_01, - output up_es_ready_01, - input up_rx_pll_rst_01, - output up_rx_pll_locked_01, - input up_rx_rst_01, - input up_rx_user_ready_01, - output up_rx_rst_done_01, - input up_rx_lpm_dfe_n_01, - input [ 2:0] up_rx_rate_01, - input [ 1:0] up_rx_sys_clk_sel_01, - input [ 2:0] up_rx_out_clk_sel_01, - input [ 7:0] up_rx_sel_01, - input up_rx_enb_01, - input [11:0] up_rx_addr_01, - input up_rx_wr_01, - input [15:0] up_rx_wdata_01, - output [15:0] up_rx_rdata_01, - output up_rx_ready_01, - input up_tx_pll_rst_01, - output up_tx_pll_locked_01, - input up_tx_rst_01, - input up_tx_user_ready_01, - output up_tx_rst_done_01, - input up_tx_lpm_dfe_n_01, - input [ 2:0] up_tx_rate_01, - input [ 1:0] up_tx_sys_clk_sel_01, - input [ 2:0] up_tx_out_clk_sel_01, - input [ 7:0] up_tx_sel_01, - input up_tx_enb_01, - input [11:0] up_tx_addr_01, - input up_tx_wr_01, - input [15:0] up_tx_wdata_01, - output [15:0] up_tx_rdata_01, - output up_tx_ready_01, + input [ 7:0] up_es_sel_1, + input up_es_enb_1, + input [11:0] up_es_addr_1, + input up_es_wr_1, + input [15:0] up_es_wdata_1, + output [15:0] up_es_rdata_1, + output up_es_ready_1, + input up_rx_pll_rst_1, + output up_rx_pll_locked_1, + input up_rx_rst_1, + input up_rx_user_ready_1, + output up_rx_rst_done_1, + input up_rx_lpm_dfe_n_1, + input [ 2:0] up_rx_rate_1, + input [ 1:0] up_rx_sys_clk_sel_1, + input [ 2:0] up_rx_out_clk_sel_1, + input [ 7:0] up_rx_sel_1, + input up_rx_enb_1, + input [11:0] up_rx_addr_1, + input up_rx_wr_1, + input [15:0] up_rx_wdata_1, + output [15:0] up_rx_rdata_1, + output up_rx_ready_1, + input up_tx_pll_rst_1, + output up_tx_pll_locked_1, + input up_tx_rst_1, + input up_tx_user_ready_1, + output up_tx_rst_done_1, + input up_tx_lpm_dfe_n_1, + input [ 2:0] up_tx_rate_1, + input [ 1:0] up_tx_sys_clk_sel_1, + input [ 2:0] up_tx_out_clk_sel_1, + input [ 7:0] up_tx_sel_1, + input up_tx_enb_1, + input [11:0] up_tx_addr_1, + input up_tx_wr_1, + input [15:0] up_tx_wdata_1, + output [15:0] up_tx_rdata_1, + output up_tx_ready_1, - input cpll_ref_clk_02, + input cpll_ref_clk_2, - input rx_02_p, - input rx_02_n, - output rx_out_clk_02, - input rx_clk_02, - output [ 3:0] rx_charisk_02, - output [ 3:0] rx_disperr_02, - output [ 3:0] rx_notintable_02, - output [31:0] rx_data_02, - input rx_calign_02, + input rx_2_p, + input rx_2_n, + output rx_out_clk_2, + input rx_clk_2, + output [ 3:0] rx_charisk_2, + output [ 3:0] rx_disperr_2, + output [ 3:0] rx_notintable_2, + output [31:0] rx_data_2, + input rx_calign_2, - output tx_02_p, - output tx_02_n, - output tx_out_clk_02, - input tx_clk_02, - input [ 3:0] tx_charisk_02, - input [31:0] tx_data_02, + output tx_2_p, + output tx_2_n, + output tx_out_clk_2, + input tx_clk_2, + input [ 3:0] tx_charisk_2, + input [31:0] tx_data_2, - input [ 7:0] up_es_sel_02, - input up_es_enb_02, - input [11:0] up_es_addr_02, - input up_es_wr_02, - input [15:0] up_es_wdata_02, - output [15:0] up_es_rdata_02, - output up_es_ready_02, - input up_rx_pll_rst_02, - output up_rx_pll_locked_02, - input up_rx_rst_02, - input up_rx_user_ready_02, - output up_rx_rst_done_02, - input up_rx_lpm_dfe_n_02, - input [ 2:0] up_rx_rate_02, - input [ 1:0] up_rx_sys_clk_sel_02, - input [ 2:0] up_rx_out_clk_sel_02, - input [ 7:0] up_rx_sel_02, - input up_rx_enb_02, - input [11:0] up_rx_addr_02, - input up_rx_wr_02, - input [15:0] up_rx_wdata_02, - output [15:0] up_rx_rdata_02, - output up_rx_ready_02, - input up_tx_pll_rst_02, - output up_tx_pll_locked_02, - input up_tx_rst_02, - input up_tx_user_ready_02, - output up_tx_rst_done_02, - input up_tx_lpm_dfe_n_02, - input [ 2:0] up_tx_rate_02, - input [ 1:0] up_tx_sys_clk_sel_02, - input [ 2:0] up_tx_out_clk_sel_02, - input [ 7:0] up_tx_sel_02, - input up_tx_enb_02, - input [11:0] up_tx_addr_02, - input up_tx_wr_02, - input [15:0] up_tx_wdata_02, - output [15:0] up_tx_rdata_02, - output up_tx_ready_02, + input [ 7:0] up_es_sel_2, + input up_es_enb_2, + input [11:0] up_es_addr_2, + input up_es_wr_2, + input [15:0] up_es_wdata_2, + output [15:0] up_es_rdata_2, + output up_es_ready_2, + input up_rx_pll_rst_2, + output up_rx_pll_locked_2, + input up_rx_rst_2, + input up_rx_user_ready_2, + output up_rx_rst_done_2, + input up_rx_lpm_dfe_n_2, + input [ 2:0] up_rx_rate_2, + input [ 1:0] up_rx_sys_clk_sel_2, + input [ 2:0] up_rx_out_clk_sel_2, + input [ 7:0] up_rx_sel_2, + input up_rx_enb_2, + input [11:0] up_rx_addr_2, + input up_rx_wr_2, + input [15:0] up_rx_wdata_2, + output [15:0] up_rx_rdata_2, + output up_rx_ready_2, + input up_tx_pll_rst_2, + output up_tx_pll_locked_2, + input up_tx_rst_2, + input up_tx_user_ready_2, + output up_tx_rst_done_2, + input up_tx_lpm_dfe_n_2, + input [ 2:0] up_tx_rate_2, + input [ 1:0] up_tx_sys_clk_sel_2, + input [ 2:0] up_tx_out_clk_sel_2, + input [ 7:0] up_tx_sel_2, + input up_tx_enb_2, + input [11:0] up_tx_addr_2, + input up_tx_wr_2, + input [15:0] up_tx_wdata_2, + output [15:0] up_tx_rdata_2, + output up_tx_ready_2, - input cpll_ref_clk_03, + input cpll_ref_clk_3, - input rx_03_p, - input rx_03_n, - output rx_out_clk_03, - input rx_clk_03, - output [ 3:0] rx_charisk_03, - output [ 3:0] rx_disperr_03, - output [ 3:0] rx_notintable_03, - output [31:0] rx_data_03, - input rx_calign_03, + input rx_3_p, + input rx_3_n, + output rx_out_clk_3, + input rx_clk_3, + output [ 3:0] rx_charisk_3, + output [ 3:0] rx_disperr_3, + output [ 3:0] rx_notintable_3, + output [31:0] rx_data_3, + input rx_calign_3, - output tx_03_p, - output tx_03_n, - output tx_out_clk_03, - input tx_clk_03, - input [ 3:0] tx_charisk_03, - input [31:0] tx_data_03, + output tx_3_p, + output tx_3_n, + output tx_out_clk_3, + input tx_clk_3, + input [ 3:0] tx_charisk_3, + input [31:0] tx_data_3, - input [ 7:0] up_es_sel_03, - input up_es_enb_03, - input [11:0] up_es_addr_03, - input up_es_wr_03, - input [15:0] up_es_wdata_03, - output [15:0] up_es_rdata_03, - output up_es_ready_03, - input up_rx_pll_rst_03, - output up_rx_pll_locked_03, - input up_rx_rst_03, - input up_rx_user_ready_03, - output up_rx_rst_done_03, - input up_rx_lpm_dfe_n_03, - input [ 2:0] up_rx_rate_03, - input [ 1:0] up_rx_sys_clk_sel_03, - input [ 2:0] up_rx_out_clk_sel_03, - input [ 7:0] up_rx_sel_03, - input up_rx_enb_03, - input [11:0] up_rx_addr_03, - input up_rx_wr_03, - input [15:0] up_rx_wdata_03, - output [15:0] up_rx_rdata_03, - output up_rx_ready_03, - input up_tx_pll_rst_03, - output up_tx_pll_locked_03, - input up_tx_rst_03, - input up_tx_user_ready_03, - output up_tx_rst_done_03, - input up_tx_lpm_dfe_n_03, - input [ 2:0] up_tx_rate_03, - input [ 1:0] up_tx_sys_clk_sel_03, - input [ 2:0] up_tx_out_clk_sel_03, - input [ 7:0] up_tx_sel_03, - input up_tx_enb_03, - input [11:0] up_tx_addr_03, - input up_tx_wr_03, - input [15:0] up_tx_wdata_03, - output [15:0] up_tx_rdata_03, - output up_tx_ready_03, + input [ 7:0] up_es_sel_3, + input up_es_enb_3, + input [11:0] up_es_addr_3, + input up_es_wr_3, + input [15:0] up_es_wdata_3, + output [15:0] up_es_rdata_3, + output up_es_ready_3, + input up_rx_pll_rst_3, + output up_rx_pll_locked_3, + input up_rx_rst_3, + input up_rx_user_ready_3, + output up_rx_rst_done_3, + input up_rx_lpm_dfe_n_3, + input [ 2:0] up_rx_rate_3, + input [ 1:0] up_rx_sys_clk_sel_3, + input [ 2:0] up_rx_out_clk_sel_3, + input [ 7:0] up_rx_sel_3, + input up_rx_enb_3, + input [11:0] up_rx_addr_3, + input up_rx_wr_3, + input [15:0] up_rx_wdata_3, + output [15:0] up_rx_rdata_3, + output up_rx_ready_3, + input up_tx_pll_rst_3, + output up_tx_pll_locked_3, + input up_tx_rst_3, + input up_tx_user_ready_3, + output up_tx_rst_done_3, + input up_tx_lpm_dfe_n_3, + input [ 2:0] up_tx_rate_3, + input [ 1:0] up_tx_sys_clk_sel_3, + input [ 2:0] up_tx_out_clk_sel_3, + input [ 7:0] up_tx_sel_3, + input up_tx_enb_3, + input [11:0] up_tx_addr_3, + input up_tx_wr_3, + input [15:0] up_tx_wdata_3, + output [15:0] up_tx_rdata_3, + output up_tx_ready_3, - input qpll_ref_clk_04, - input cpll_ref_clk_04, + input qpll_ref_clk_4, + input cpll_ref_clk_4, - input rx_04_p, - input rx_04_n, - output rx_out_clk_04, - input rx_clk_04, - output [ 3:0] rx_charisk_04, - output [ 3:0] rx_disperr_04, - output [ 3:0] rx_notintable_04, - output [31:0] rx_data_04, - input rx_calign_04, + input rx_4_p, + input rx_4_n, + output rx_out_clk_4, + input rx_clk_4, + output [ 3:0] rx_charisk_4, + output [ 3:0] rx_disperr_4, + output [ 3:0] rx_notintable_4, + output [31:0] rx_data_4, + input rx_calign_4, - output tx_04_p, - output tx_04_n, - output tx_out_clk_04, - input tx_clk_04, - input [ 3:0] tx_charisk_04, - input [31:0] tx_data_04, + output tx_4_p, + output tx_4_n, + output tx_out_clk_4, + input tx_clk_4, + input [ 3:0] tx_charisk_4, + input [31:0] tx_data_4, - input [ 7:0] up_cm_sel_04, - input up_cm_enb_04, - input [11:0] up_cm_addr_04, - input up_cm_wr_04, - input [15:0] up_cm_wdata_04, - output [15:0] up_cm_rdata_04, - output up_cm_ready_04, - input [ 7:0] up_es_sel_04, - input up_es_enb_04, - input [11:0] up_es_addr_04, - input up_es_wr_04, - input [15:0] up_es_wdata_04, - output [15:0] up_es_rdata_04, - output up_es_ready_04, - input up_rx_pll_rst_04, - output up_rx_pll_locked_04, - input up_rx_rst_04, - input up_rx_user_ready_04, - output up_rx_rst_done_04, - input up_rx_lpm_dfe_n_04, - input [ 2:0] up_rx_rate_04, - input [ 1:0] up_rx_sys_clk_sel_04, - input [ 2:0] up_rx_out_clk_sel_04, - input [ 7:0] up_rx_sel_04, - input up_rx_enb_04, - input [11:0] up_rx_addr_04, - input up_rx_wr_04, - input [15:0] up_rx_wdata_04, - output [15:0] up_rx_rdata_04, - output up_rx_ready_04, - input up_tx_pll_rst_04, - output up_tx_pll_locked_04, - input up_tx_rst_04, - input up_tx_user_ready_04, - output up_tx_rst_done_04, - input up_tx_lpm_dfe_n_04, - input [ 2:0] up_tx_rate_04, - input [ 1:0] up_tx_sys_clk_sel_04, - input [ 2:0] up_tx_out_clk_sel_04, - input [ 7:0] up_tx_sel_04, - input up_tx_enb_04, - input [11:0] up_tx_addr_04, - input up_tx_wr_04, - input [15:0] up_tx_wdata_04, - output [15:0] up_tx_rdata_04, - output up_tx_ready_04, + input [ 7:0] up_cm_sel_4, + input up_cm_enb_4, + input [11:0] up_cm_addr_4, + input up_cm_wr_4, + input [15:0] up_cm_wdata_4, + output [15:0] up_cm_rdata_4, + output up_cm_ready_4, + input [ 7:0] up_es_sel_4, + input up_es_enb_4, + input [11:0] up_es_addr_4, + input up_es_wr_4, + input [15:0] up_es_wdata_4, + output [15:0] up_es_rdata_4, + output up_es_ready_4, + input up_rx_pll_rst_4, + output up_rx_pll_locked_4, + input up_rx_rst_4, + input up_rx_user_ready_4, + output up_rx_rst_done_4, + input up_rx_lpm_dfe_n_4, + input [ 2:0] up_rx_rate_4, + input [ 1:0] up_rx_sys_clk_sel_4, + input [ 2:0] up_rx_out_clk_sel_4, + input [ 7:0] up_rx_sel_4, + input up_rx_enb_4, + input [11:0] up_rx_addr_4, + input up_rx_wr_4, + input [15:0] up_rx_wdata_4, + output [15:0] up_rx_rdata_4, + output up_rx_ready_4, + input up_tx_pll_rst_4, + output up_tx_pll_locked_4, + input up_tx_rst_4, + input up_tx_user_ready_4, + output up_tx_rst_done_4, + input up_tx_lpm_dfe_n_4, + input [ 2:0] up_tx_rate_4, + input [ 1:0] up_tx_sys_clk_sel_4, + input [ 2:0] up_tx_out_clk_sel_4, + input [ 7:0] up_tx_sel_4, + input up_tx_enb_4, + input [11:0] up_tx_addr_4, + input up_tx_wr_4, + input [15:0] up_tx_wdata_4, + output [15:0] up_tx_rdata_4, + output up_tx_ready_4, - input cpll_ref_clk_05, + input cpll_ref_clk_5, - input rx_05_p, - input rx_05_n, - output rx_out_clk_05, - input rx_clk_05, - output [ 3:0] rx_charisk_05, - output [ 3:0] rx_disperr_05, - output [ 3:0] rx_notintable_05, - output [31:0] rx_data_05, - input rx_calign_05, + input rx_5_p, + input rx_5_n, + output rx_out_clk_5, + input rx_clk_5, + output [ 3:0] rx_charisk_5, + output [ 3:0] rx_disperr_5, + output [ 3:0] rx_notintable_5, + output [31:0] rx_data_5, + input rx_calign_5, - output tx_05_p, - output tx_05_n, - output tx_out_clk_05, - input tx_clk_05, - input [ 3:0] tx_charisk_05, - input [31:0] tx_data_05, + output tx_5_p, + output tx_5_n, + output tx_out_clk_5, + input tx_clk_5, + input [ 3:0] tx_charisk_5, + input [31:0] tx_data_5, - input [ 7:0] up_es_sel_05, - input up_es_enb_05, - input [11:0] up_es_addr_05, - input up_es_wr_05, - input [15:0] up_es_wdata_05, - output [15:0] up_es_rdata_05, - output up_es_ready_05, - input up_rx_pll_rst_05, - output up_rx_pll_locked_05, - input up_rx_rst_05, - input up_rx_user_ready_05, - output up_rx_rst_done_05, - input up_rx_lpm_dfe_n_05, - input [ 2:0] up_rx_rate_05, - input [ 1:0] up_rx_sys_clk_sel_05, - input [ 2:0] up_rx_out_clk_sel_05, - input [ 7:0] up_rx_sel_05, - input up_rx_enb_05, - input [11:0] up_rx_addr_05, - input up_rx_wr_05, - input [15:0] up_rx_wdata_05, - output [15:0] up_rx_rdata_05, - output up_rx_ready_05, - input up_tx_pll_rst_05, - output up_tx_pll_locked_05, - input up_tx_rst_05, - input up_tx_user_ready_05, - output up_tx_rst_done_05, - input up_tx_lpm_dfe_n_05, - input [ 2:0] up_tx_rate_05, - input [ 1:0] up_tx_sys_clk_sel_05, - input [ 2:0] up_tx_out_clk_sel_05, - input [ 7:0] up_tx_sel_05, - input up_tx_enb_05, - input [11:0] up_tx_addr_05, - input up_tx_wr_05, - input [15:0] up_tx_wdata_05, - output [15:0] up_tx_rdata_05, - output up_tx_ready_05, + input [ 7:0] up_es_sel_5, + input up_es_enb_5, + input [11:0] up_es_addr_5, + input up_es_wr_5, + input [15:0] up_es_wdata_5, + output [15:0] up_es_rdata_5, + output up_es_ready_5, + input up_rx_pll_rst_5, + output up_rx_pll_locked_5, + input up_rx_rst_5, + input up_rx_user_ready_5, + output up_rx_rst_done_5, + input up_rx_lpm_dfe_n_5, + input [ 2:0] up_rx_rate_5, + input [ 1:0] up_rx_sys_clk_sel_5, + input [ 2:0] up_rx_out_clk_sel_5, + input [ 7:0] up_rx_sel_5, + input up_rx_enb_5, + input [11:0] up_rx_addr_5, + input up_rx_wr_5, + input [15:0] up_rx_wdata_5, + output [15:0] up_rx_rdata_5, + output up_rx_ready_5, + input up_tx_pll_rst_5, + output up_tx_pll_locked_5, + input up_tx_rst_5, + input up_tx_user_ready_5, + output up_tx_rst_done_5, + input up_tx_lpm_dfe_n_5, + input [ 2:0] up_tx_rate_5, + input [ 1:0] up_tx_sys_clk_sel_5, + input [ 2:0] up_tx_out_clk_sel_5, + input [ 7:0] up_tx_sel_5, + input up_tx_enb_5, + input [11:0] up_tx_addr_5, + input up_tx_wr_5, + input [15:0] up_tx_wdata_5, + output [15:0] up_tx_rdata_5, + output up_tx_ready_5, - input cpll_ref_clk_06, + input cpll_ref_clk_6, - input rx_06_p, - input rx_06_n, - output rx_out_clk_06, - input rx_clk_06, - output [ 3:0] rx_charisk_06, - output [ 3:0] rx_disperr_06, - output [ 3:0] rx_notintable_06, - output [31:0] rx_data_06, - input rx_calign_06, + input rx_6_p, + input rx_6_n, + output rx_out_clk_6, + input rx_clk_6, + output [ 3:0] rx_charisk_6, + output [ 3:0] rx_disperr_6, + output [ 3:0] rx_notintable_6, + output [31:0] rx_data_6, + input rx_calign_6, - output tx_06_p, - output tx_06_n, - output tx_out_clk_06, - input tx_clk_06, - input [ 3:0] tx_charisk_06, - input [31:0] tx_data_06, + output tx_6_p, + output tx_6_n, + output tx_out_clk_6, + input tx_clk_6, + input [ 3:0] tx_charisk_6, + input [31:0] tx_data_6, - input [ 7:0] up_es_sel_06, - input up_es_enb_06, - input [11:0] up_es_addr_06, - input up_es_wr_06, - input [15:0] up_es_wdata_06, - output [15:0] up_es_rdata_06, - output up_es_ready_06, - input up_rx_pll_rst_06, - output up_rx_pll_locked_06, - input up_rx_rst_06, - input up_rx_user_ready_06, - output up_rx_rst_done_06, - input up_rx_lpm_dfe_n_06, - input [ 2:0] up_rx_rate_06, - input [ 1:0] up_rx_sys_clk_sel_06, - input [ 2:0] up_rx_out_clk_sel_06, - input [ 7:0] up_rx_sel_06, - input up_rx_enb_06, - input [11:0] up_rx_addr_06, - input up_rx_wr_06, - input [15:0] up_rx_wdata_06, - output [15:0] up_rx_rdata_06, - output up_rx_ready_06, - input up_tx_pll_rst_06, - output up_tx_pll_locked_06, - input up_tx_rst_06, - input up_tx_user_ready_06, - output up_tx_rst_done_06, - input up_tx_lpm_dfe_n_06, - input [ 2:0] up_tx_rate_06, - input [ 1:0] up_tx_sys_clk_sel_06, - input [ 2:0] up_tx_out_clk_sel_06, - input [ 7:0] up_tx_sel_06, - input up_tx_enb_06, - input [11:0] up_tx_addr_06, - input up_tx_wr_06, - input [15:0] up_tx_wdata_06, - output [15:0] up_tx_rdata_06, - output up_tx_ready_06, + input [ 7:0] up_es_sel_6, + input up_es_enb_6, + input [11:0] up_es_addr_6, + input up_es_wr_6, + input [15:0] up_es_wdata_6, + output [15:0] up_es_rdata_6, + output up_es_ready_6, + input up_rx_pll_rst_6, + output up_rx_pll_locked_6, + input up_rx_rst_6, + input up_rx_user_ready_6, + output up_rx_rst_done_6, + input up_rx_lpm_dfe_n_6, + input [ 2:0] up_rx_rate_6, + input [ 1:0] up_rx_sys_clk_sel_6, + input [ 2:0] up_rx_out_clk_sel_6, + input [ 7:0] up_rx_sel_6, + input up_rx_enb_6, + input [11:0] up_rx_addr_6, + input up_rx_wr_6, + input [15:0] up_rx_wdata_6, + output [15:0] up_rx_rdata_6, + output up_rx_ready_6, + input up_tx_pll_rst_6, + output up_tx_pll_locked_6, + input up_tx_rst_6, + input up_tx_user_ready_6, + output up_tx_rst_done_6, + input up_tx_lpm_dfe_n_6, + input [ 2:0] up_tx_rate_6, + input [ 1:0] up_tx_sys_clk_sel_6, + input [ 2:0] up_tx_out_clk_sel_6, + input [ 7:0] up_tx_sel_6, + input up_tx_enb_6, + input [11:0] up_tx_addr_6, + input up_tx_wr_6, + input [15:0] up_tx_wdata_6, + output [15:0] up_tx_rdata_6, + output up_tx_ready_6, - input cpll_ref_clk_07, + input cpll_ref_clk_7, - input rx_07_p, - input rx_07_n, - output rx_out_clk_07, - input rx_clk_07, - output [ 3:0] rx_charisk_07, - output [ 3:0] rx_disperr_07, - output [ 3:0] rx_notintable_07, - output [31:0] rx_data_07, - input rx_calign_07, + input rx_7_p, + input rx_7_n, + output rx_out_clk_7, + input rx_clk_7, + output [ 3:0] rx_charisk_7, + output [ 3:0] rx_disperr_7, + output [ 3:0] rx_notintable_7, + output [31:0] rx_data_7, + input rx_calign_7, - output tx_07_p, - output tx_07_n, - output tx_out_clk_07, - input tx_clk_07, - input [ 3:0] tx_charisk_07, - input [31:0] tx_data_07, + output tx_7_p, + output tx_7_n, + output tx_out_clk_7, + input tx_clk_7, + input [ 3:0] tx_charisk_7, + input [31:0] tx_data_7, - input [ 7:0] up_es_sel_07, - input up_es_enb_07, - input [11:0] up_es_addr_07, - input up_es_wr_07, - input [15:0] up_es_wdata_07, - output [15:0] up_es_rdata_07, - output up_es_ready_07, - input up_rx_pll_rst_07, - output up_rx_pll_locked_07, - input up_rx_rst_07, - input up_rx_user_ready_07, - output up_rx_rst_done_07, - input up_rx_lpm_dfe_n_07, - input [ 2:0] up_rx_rate_07, - input [ 1:0] up_rx_sys_clk_sel_07, - input [ 2:0] up_rx_out_clk_sel_07, - input [ 7:0] up_rx_sel_07, - input up_rx_enb_07, - input [11:0] up_rx_addr_07, - input up_rx_wr_07, - input [15:0] up_rx_wdata_07, - output [15:0] up_rx_rdata_07, - output up_rx_ready_07, - input up_tx_pll_rst_07, - output up_tx_pll_locked_07, - input up_tx_rst_07, - input up_tx_user_ready_07, - output up_tx_rst_done_07, - input up_tx_lpm_dfe_n_07, - input [ 2:0] up_tx_rate_07, - input [ 1:0] up_tx_sys_clk_sel_07, - input [ 2:0] up_tx_out_clk_sel_07, - input [ 7:0] up_tx_sel_07, - input up_tx_enb_07, - input [11:0] up_tx_addr_07, - input up_tx_wr_07, - input [15:0] up_tx_wdata_07, - output [15:0] up_tx_rdata_07, - output up_tx_ready_07, + input [ 7:0] up_es_sel_7, + input up_es_enb_7, + input [11:0] up_es_addr_7, + input up_es_wr_7, + input [15:0] up_es_wdata_7, + output [15:0] up_es_rdata_7, + output up_es_ready_7, + input up_rx_pll_rst_7, + output up_rx_pll_locked_7, + input up_rx_rst_7, + input up_rx_user_ready_7, + output up_rx_rst_done_7, + input up_rx_lpm_dfe_n_7, + input [ 2:0] up_rx_rate_7, + input [ 1:0] up_rx_sys_clk_sel_7, + input [ 2:0] up_rx_out_clk_sel_7, + input [ 7:0] up_rx_sel_7, + input up_rx_enb_7, + input [11:0] up_rx_addr_7, + input up_rx_wr_7, + input [15:0] up_rx_wdata_7, + output [15:0] up_rx_rdata_7, + output up_rx_ready_7, + input up_tx_pll_rst_7, + output up_tx_pll_locked_7, + input up_tx_rst_7, + input up_tx_user_ready_7, + output up_tx_rst_done_7, + input up_tx_lpm_dfe_n_7, + input [ 2:0] up_tx_rate_7, + input [ 1:0] up_tx_sys_clk_sel_7, + input [ 2:0] up_tx_out_clk_sel_7, + input [ 7:0] up_tx_sel_7, + input up_tx_enb_7, + input [11:0] up_tx_addr_7, + input up_tx_wr_7, + input [15:0] up_tx_wdata_7, + output [15:0] up_tx_rdata_7, + output up_tx_ready_7, - input qpll_ref_clk_08, - input cpll_ref_clk_08, + input qpll_ref_clk_8, + input cpll_ref_clk_8, - input rx_08_p, - input rx_08_n, - output rx_out_clk_08, - input rx_clk_08, - output [ 3:0] rx_charisk_08, - output [ 3:0] rx_disperr_08, - output [ 3:0] rx_notintable_08, - output [31:0] rx_data_08, - input rx_calign_08, + input rx_8_p, + input rx_8_n, + output rx_out_clk_8, + input rx_clk_8, + output [ 3:0] rx_charisk_8, + output [ 3:0] rx_disperr_8, + output [ 3:0] rx_notintable_8, + output [31:0] rx_data_8, + input rx_calign_8, - output tx_08_p, - output tx_08_n, - output tx_out_clk_08, - input tx_clk_08, - input [ 3:0] tx_charisk_08, - input [31:0] tx_data_08, + output tx_8_p, + output tx_8_n, + output tx_out_clk_8, + input tx_clk_8, + input [ 3:0] tx_charisk_8, + input [31:0] tx_data_8, - input [ 7:0] up_cm_sel_08, - input up_cm_enb_08, - input [11:0] up_cm_addr_08, - input up_cm_wr_08, - input [15:0] up_cm_wdata_08, - output [15:0] up_cm_rdata_08, - output up_cm_ready_08, - input [ 7:0] up_es_sel_08, - input up_es_enb_08, - input [11:0] up_es_addr_08, - input up_es_wr_08, - input [15:0] up_es_wdata_08, - output [15:0] up_es_rdata_08, - output up_es_ready_08, - input up_rx_pll_rst_08, - output up_rx_pll_locked_08, - input up_rx_rst_08, - input up_rx_user_ready_08, - output up_rx_rst_done_08, - input up_rx_lpm_dfe_n_08, - input [ 2:0] up_rx_rate_08, - input [ 1:0] up_rx_sys_clk_sel_08, - input [ 2:0] up_rx_out_clk_sel_08, - input [ 7:0] up_rx_sel_08, - input up_rx_enb_08, - input [11:0] up_rx_addr_08, - input up_rx_wr_08, - input [15:0] up_rx_wdata_08, - output [15:0] up_rx_rdata_08, - output up_rx_ready_08, - input up_tx_pll_rst_08, - output up_tx_pll_locked_08, - input up_tx_rst_08, - input up_tx_user_ready_08, - output up_tx_rst_done_08, - input up_tx_lpm_dfe_n_08, - input [ 2:0] up_tx_rate_08, - input [ 1:0] up_tx_sys_clk_sel_08, - input [ 2:0] up_tx_out_clk_sel_08, - input [ 7:0] up_tx_sel_08, - input up_tx_enb_08, - input [11:0] up_tx_addr_08, - input up_tx_wr_08, - input [15:0] up_tx_wdata_08, - output [15:0] up_tx_rdata_08, - output up_tx_ready_08, + input [ 7:0] up_cm_sel_8, + input up_cm_enb_8, + input [11:0] up_cm_addr_8, + input up_cm_wr_8, + input [15:0] up_cm_wdata_8, + output [15:0] up_cm_rdata_8, + output up_cm_ready_8, + input [ 7:0] up_es_sel_8, + input up_es_enb_8, + input [11:0] up_es_addr_8, + input up_es_wr_8, + input [15:0] up_es_wdata_8, + output [15:0] up_es_rdata_8, + output up_es_ready_8, + input up_rx_pll_rst_8, + output up_rx_pll_locked_8, + input up_rx_rst_8, + input up_rx_user_ready_8, + output up_rx_rst_done_8, + input up_rx_lpm_dfe_n_8, + input [ 2:0] up_rx_rate_8, + input [ 1:0] up_rx_sys_clk_sel_8, + input [ 2:0] up_rx_out_clk_sel_8, + input [ 7:0] up_rx_sel_8, + input up_rx_enb_8, + input [11:0] up_rx_addr_8, + input up_rx_wr_8, + input [15:0] up_rx_wdata_8, + output [15:0] up_rx_rdata_8, + output up_rx_ready_8, + input up_tx_pll_rst_8, + output up_tx_pll_locked_8, + input up_tx_rst_8, + input up_tx_user_ready_8, + output up_tx_rst_done_8, + input up_tx_lpm_dfe_n_8, + input [ 2:0] up_tx_rate_8, + input [ 1:0] up_tx_sys_clk_sel_8, + input [ 2:0] up_tx_out_clk_sel_8, + input [ 7:0] up_tx_sel_8, + input up_tx_enb_8, + input [11:0] up_tx_addr_8, + input up_tx_wr_8, + input [15:0] up_tx_wdata_8, + output [15:0] up_tx_rdata_8, + output up_tx_ready_8, - input cpll_ref_clk_09, + input cpll_ref_clk_9, - input rx_09_p, - input rx_09_n, - output rx_out_clk_09, - input rx_clk_09, - output [ 3:0] rx_charisk_09, - output [ 3:0] rx_disperr_09, - output [ 3:0] rx_notintable_09, - output [31:0] rx_data_09, - input rx_calign_09, + input rx_9_p, + input rx_9_n, + output rx_out_clk_9, + input rx_clk_9, + output [ 3:0] rx_charisk_9, + output [ 3:0] rx_disperr_9, + output [ 3:0] rx_notintable_9, + output [31:0] rx_data_9, + input rx_calign_9, - output tx_09_p, - output tx_09_n, - output tx_out_clk_09, - input tx_clk_09, - input [ 3:0] tx_charisk_09, - input [31:0] tx_data_09, + output tx_9_p, + output tx_9_n, + output tx_out_clk_9, + input tx_clk_9, + input [ 3:0] tx_charisk_9, + input [31:0] tx_data_9, - input [ 7:0] up_es_sel_09, - input up_es_enb_09, - input [11:0] up_es_addr_09, - input up_es_wr_09, - input [15:0] up_es_wdata_09, - output [15:0] up_es_rdata_09, - output up_es_ready_09, - input up_rx_pll_rst_09, - output up_rx_pll_locked_09, - input up_rx_rst_09, - input up_rx_user_ready_09, - output up_rx_rst_done_09, - input up_rx_lpm_dfe_n_09, - input [ 2:0] up_rx_rate_09, - input [ 1:0] up_rx_sys_clk_sel_09, - input [ 2:0] up_rx_out_clk_sel_09, - input [ 7:0] up_rx_sel_09, - input up_rx_enb_09, - input [11:0] up_rx_addr_09, - input up_rx_wr_09, - input [15:0] up_rx_wdata_09, - output [15:0] up_rx_rdata_09, - output up_rx_ready_09, - input up_tx_pll_rst_09, - output up_tx_pll_locked_09, - input up_tx_rst_09, - input up_tx_user_ready_09, - output up_tx_rst_done_09, - input up_tx_lpm_dfe_n_09, - input [ 2:0] up_tx_rate_09, - input [ 1:0] up_tx_sys_clk_sel_09, - input [ 2:0] up_tx_out_clk_sel_09, - input [ 7:0] up_tx_sel_09, - input up_tx_enb_09, - input [11:0] up_tx_addr_09, - input up_tx_wr_09, - input [15:0] up_tx_wdata_09, - output [15:0] up_tx_rdata_09, - output up_tx_ready_09, + input [ 7:0] up_es_sel_9, + input up_es_enb_9, + input [11:0] up_es_addr_9, + input up_es_wr_9, + input [15:0] up_es_wdata_9, + output [15:0] up_es_rdata_9, + output up_es_ready_9, + input up_rx_pll_rst_9, + output up_rx_pll_locked_9, + input up_rx_rst_9, + input up_rx_user_ready_9, + output up_rx_rst_done_9, + input up_rx_lpm_dfe_n_9, + input [ 2:0] up_rx_rate_9, + input [ 1:0] up_rx_sys_clk_sel_9, + input [ 2:0] up_rx_out_clk_sel_9, + input [ 7:0] up_rx_sel_9, + input up_rx_enb_9, + input [11:0] up_rx_addr_9, + input up_rx_wr_9, + input [15:0] up_rx_wdata_9, + output [15:0] up_rx_rdata_9, + output up_rx_ready_9, + input up_tx_pll_rst_9, + output up_tx_pll_locked_9, + input up_tx_rst_9, + input up_tx_user_ready_9, + output up_tx_rst_done_9, + input up_tx_lpm_dfe_n_9, + input [ 2:0] up_tx_rate_9, + input [ 1:0] up_tx_sys_clk_sel_9, + input [ 2:0] up_tx_out_clk_sel_9, + input [ 7:0] up_tx_sel_9, + input up_tx_enb_9, + input [11:0] up_tx_addr_9, + input up_tx_wr_9, + input [15:0] up_tx_wdata_9, + output [15:0] up_tx_rdata_9, + output up_tx_ready_9, input cpll_ref_clk_10, @@ -1020,7 +1021,8 @@ module util_adxcvr ( // parameters - parameter integer XCVR_ID = 0; + parameter integer RX_NUM_OF_LANES = 8; + parameter integer TX_NUM_OF_LANES = 8; parameter integer GTH_OR_GTX_N = 0; parameter integer CPLL_TX_OR_RX_N = 0; parameter integer CPLL_FBDIV = 2; @@ -1037,20 +1039,23 @@ module util_adxcvr ( parameter [26:0] QPLL_CFG = 27'h06801C1; parameter [ 9:0] QPLL_FBDIV = 10'b0000110000; + localparam integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ? + TX_NUM_OF_LANES : RX_NUM_OF_LANES; + // internal signals - wire qpll2ch_clk_00; - wire qpll2ch_ref_clk_00; - wire qpll2ch_locked_00; - wire up_qpll_rst_00; - wire qpll2ch_clk_04; - wire qpll2ch_ref_clk_04; - wire qpll2ch_locked_04; - wire up_qpll_rst_04; - wire qpll2ch_clk_08; - wire qpll2ch_ref_clk_08; - wire qpll2ch_locked_08; - wire up_qpll_rst_08; + wire qpll2ch_clk_0; + wire qpll2ch_ref_clk_0; + wire qpll2ch_locked_0; + wire up_qpll_rst_0; + wire qpll2ch_clk_4; + wire qpll2ch_ref_clk_4; + wire qpll2ch_locked_4; + wire up_qpll_rst_4; + wire qpll2ch_clk_8; + wire qpll2ch_ref_clk_8; + wire qpll2ch_locked_8; + wire up_qpll_rst_8; wire qpll2ch_clk_12; wire qpll2ch_ref_clk_12; wire qpll2ch_locked_12; @@ -1058,44 +1063,50 @@ module util_adxcvr ( // quad controls - assign up_qpll_rst_00 = (CPLL_TX_OR_RX_N == 0) ? up_tx_00.pll_rst : up_rx_00.pll_rst; - assign up_qpll_rst_04 = (CPLL_TX_OR_RX_N == 0) ? up_tx_04.pll_rst : up_rx_04.pll_rst; - assign up_qpll_rst_08 = (CPLL_TX_OR_RX_N == 0) ? up_tx_08.pll_rst : up_rx_08.pll_rst; - assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_12.pll_rst : up_rx_12.pll_rst; + assign up_qpll_rst_0 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_0 : up_rx_pll_rst_0; + assign up_qpll_rst_4 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_4 : up_rx_pll_rst_4; + assign up_qpll_rst_8 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_8 : up_rx_pll_rst_8; + assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_12 : up_rx_pll_rst_12; // instantiations generate if (NUM_OF_LANES >= 1) begin util_adxcvr_xcm #( - .XCVR_ID (n), + .XCVR_ID (0), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) - i_xcm_00 ( - .qpll_ref_clk (qpll_ref_clk_00), - .qpll2ch_clk (qpll2ch_clk_00), - .qpll2ch_ref_clk (qpll2ch_ref_clk_00), - .qpll2ch_locked (qpll2ch_locked_00), + i_xcm_0 ( + .qpll_ref_clk (qpll_ref_clk_0), + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), .up_rstn (up_rstn), .up_clk (up_clk), - .up_qpll_rst (up_qpll_rst_00), - .up_cm_sel (up_cm_sel_00), - .up_cm_enb (up_cm_enb_00), - .up_cm_addr (up_cm_addr_00), - .up_cm_wr (up_cm_wr_00), - .up_cm_wdata (up_cm_wdata_00), - .up_cm_rdata (up_cm_rdata_00), - .up_cm_ready (up_cm_ready_00)); + .up_qpll_rst (up_qpll_rst_0), + .up_cm_sel (up_cm_sel_0), + .up_cm_enb (up_cm_enb_0), + .up_cm_addr (up_cm_addr_0), + .up_cm_wr (up_cm_wr_0), + .up_cm_wdata (up_cm_wdata_0), + .up_cm_rdata (up_cm_rdata_0), + .up_cm_ready (up_cm_ready_0)); + end else begin + assign qpll2ch_clk_0 = 1'd0; + assign qpll2ch_ref_clk_0 = 1'd0; + assign qpll2ch_locked_0 = 1'd0; + assign up_cm_rdata_0 = 16'd0; + assign up_cm_ready_0 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 1) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (0), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1107,74 +1118,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_00 ( - .qpll2ch_clk (qpll2ch_clk_00), - .qpll2ch_ref_clk (qpll2ch_ref_clk_00), - .qpll2ch_locked (qpll2ch_locked_00), - .cpll_ref_clk (cpll_ref_clk_00), - .rx_p (rx_00_p), - .rx_n (rx_00_n), - .rx_out_clk (rx_out_clk_00), - .rx_clk (rx_clk_00), - .rx_charisk (rx_charisk_00), - .rx_disperr (rx_disperr_00), - .rx_notintable (rx_notintable_00), - .rx_data (rx_data_00), - .rx_calign (rx_calign_00), - .tx_p (tx_00_p), - .tx_n (tx_00_n), - .tx_out_clk (tx_out_clk_00), - .tx_clk (tx_clk_00), - .tx_charisk (tx_charisk_00), - .tx_data (tx_data_00), + i_xch_0 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_0), + .rx_p (rx_0_p), + .rx_n (rx_0_n), + .rx_out_clk (rx_out_clk_0), + .rx_clk (rx_clk_0), + .rx_charisk (rx_charisk_0), + .rx_disperr (rx_disperr_0), + .rx_notintable (rx_notintable_0), + .rx_data (rx_data_0), + .rx_calign (rx_calign_0), + .tx_p (tx_0_p), + .tx_n (tx_0_n), + .tx_out_clk (tx_out_clk_0), + .tx_clk (tx_clk_0), + .tx_charisk (tx_charisk_0), + .tx_data (tx_data_0), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_00), - .up_es_enb (up_es_enb_00), - .up_es_addr (up_es_addr_00), - .up_es_wr (up_es_wr_00), - .up_es_wdata (up_es_wdata_00), - .up_es_rdata (up_es_rdata_00), - .up_es_ready (up_es_ready_00), - .up_rx_pll_rst (up_rx_pll_rst_00), - .up_rx_pll_locked (up_rx_pll_locked_00), - .up_rx_rst (up_rx_rst_00), - .up_rx_user_ready (up_rx_user_ready_00), - .up_rx_rst_done (up_rx_rst_done_00), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_00), - .up_rx_rate (up_rx_rate_00), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_00), - .up_rx_out_clk_sel (up_rx_out_clk_sel_00), - .up_rx_sel (up_rx_sel_00), - .up_rx_enb (up_rx_enb_00), - .up_rx_addr (up_rx_addr_00), - .up_rx_wr (up_rx_wr_00), - .up_rx_wdata (up_rx_wdata_00), - .up_rx_rdata (up_rx_rdata_00), - .up_rx_ready (up_rx_ready_00), - .up_tx_pll_rst (up_tx_pll_rst_00), - .up_tx_pll_locked (up_tx_pll_locked_00), - .up_tx_rst (up_tx_rst_00), - .up_tx_user_ready (up_tx_user_ready_00), - .up_tx_rst_done (up_tx_rst_done_00), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_00), - .up_tx_rate (up_tx_rate_00), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_00), - .up_tx_out_clk_sel (up_tx_out_clk_sel_00), - .up_tx_sel (up_tx_sel_00), - .up_tx_enb (up_tx_enb_00), - .up_tx_addr (up_tx_addr_00), - .up_tx_wr (up_tx_wr_00), - .up_tx_wdata (up_tx_wdata_00), - .up_tx_rdata (up_tx_rdata_00), - .up_tx_ready (up_tx_ready_00)); + .up_es_sel (up_es_sel_0), + .up_es_enb (up_es_enb_0), + .up_es_addr (up_es_addr_0), + .up_es_wr (up_es_wr_0), + .up_es_wdata (up_es_wdata_0), + .up_es_rdata (up_es_rdata_0), + .up_es_ready (up_es_ready_0), + .up_rx_pll_rst (up_rx_pll_rst_0), + .up_rx_pll_locked (up_rx_pll_locked_0), + .up_rx_rst (up_rx_rst_0), + .up_rx_user_ready (up_rx_user_ready_0), + .up_rx_rst_done (up_rx_rst_done_0), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0), + .up_rx_rate (up_rx_rate_0), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_0), + .up_rx_out_clk_sel (up_rx_out_clk_sel_0), + .up_rx_sel (up_rx_sel_0), + .up_rx_enb (up_rx_enb_0), + .up_rx_addr (up_rx_addr_0), + .up_rx_wr (up_rx_wr_0), + .up_rx_wdata (up_rx_wdata_0), + .up_rx_rdata (up_rx_rdata_0), + .up_rx_ready (up_rx_ready_0), + .up_tx_pll_rst (up_tx_pll_rst_0), + .up_tx_pll_locked (up_tx_pll_locked_0), + .up_tx_rst (up_tx_rst_0), + .up_tx_user_ready (up_tx_user_ready_0), + .up_tx_rst_done (up_tx_rst_done_0), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0), + .up_tx_rate (up_tx_rate_0), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_0), + .up_tx_out_clk_sel (up_tx_out_clk_sel_0), + .up_tx_sel (up_tx_sel_0), + .up_tx_enb (up_tx_enb_0), + .up_tx_addr (up_tx_addr_0), + .up_tx_wr (up_tx_wr_0), + .up_tx_wdata (up_tx_wdata_0), + .up_tx_rdata (up_tx_rdata_0), + .up_tx_ready (up_tx_ready_0)); + end else begin + assign rx_out_clk_0 = 1'd0; + assign rx_charisk_0 = 4'd0; + assign rx_disperr_0 = 4'd0; + assign rx_notintable_0 = 4'd0; + assign rx_data_0 = 32'd0; + assign tx_0_p = 1'd0; + assign tx_0_n = 1'd0; + assign tx_out_clk_0 = 1'd0; + assign up_es_rdata_0 = 16'd0; + assign up_es_ready_0 = 1'd0; + assign up_rx_pll_locked_0 = 1'd0; + assign up_rx_rst_done_0 = 1'd0; + assign up_rx_rdata_0 = 16'd0; + assign up_rx_ready_0 = 1'd0; + assign up_tx_pll_locked_0 = 1'd0; + assign up_tx_rst_done_0 = 1'd0; + assign up_tx_rdata_0 = 16'd0; + assign up_tx_ready_0 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 2) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (1), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1186,74 +1217,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_01 ( - .qpll2ch_clk (qpll2ch_clk_00), - .qpll2ch_ref_clk (qpll2ch_ref_clk_00), - .qpll2ch_locked (qpll2ch_locked_00), - .cpll_ref_clk (cpll_ref_clk_01), - .rx_p (rx_01_p), - .rx_n (rx_01_n), - .rx_out_clk (rx_out_clk_01), - .rx_clk (rx_clk_01), - .rx_charisk (rx_charisk_01), - .rx_disperr (rx_disperr_01), - .rx_notintable (rx_notintable_01), - .rx_data (rx_data_01), - .rx_calign (rx_calign_01), - .tx_p (tx_01_p), - .tx_n (tx_01_n), - .tx_out_clk (tx_out_clk_01), - .tx_clk (tx_clk_01), - .tx_charisk (tx_charisk_01), - .tx_data (tx_data_01), + i_xch_1 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_1), + .rx_p (rx_1_p), + .rx_n (rx_1_n), + .rx_out_clk (rx_out_clk_1), + .rx_clk (rx_clk_1), + .rx_charisk (rx_charisk_1), + .rx_disperr (rx_disperr_1), + .rx_notintable (rx_notintable_1), + .rx_data (rx_data_1), + .rx_calign (rx_calign_1), + .tx_p (tx_1_p), + .tx_n (tx_1_n), + .tx_out_clk (tx_out_clk_1), + .tx_clk (tx_clk_1), + .tx_charisk (tx_charisk_1), + .tx_data (tx_data_1), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_01), - .up_es_enb (up_es_enb_01), - .up_es_addr (up_es_addr_01), - .up_es_wr (up_es_wr_01), - .up_es_wdata (up_es_wdata_01), - .up_es_rdata (up_es_rdata_01), - .up_es_ready (up_es_ready_01), - .up_rx_pll_rst (up_rx_pll_rst_01), - .up_rx_pll_locked (up_rx_pll_locked_01), - .up_rx_rst (up_rx_rst_01), - .up_rx_user_ready (up_rx_user_ready_01), - .up_rx_rst_done (up_rx_rst_done_01), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_01), - .up_rx_rate (up_rx_rate_01), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_01), - .up_rx_out_clk_sel (up_rx_out_clk_sel_01), - .up_rx_sel (up_rx_sel_01), - .up_rx_enb (up_rx_enb_01), - .up_rx_addr (up_rx_addr_01), - .up_rx_wr (up_rx_wr_01), - .up_rx_wdata (up_rx_wdata_01), - .up_rx_rdata (up_rx_rdata_01), - .up_rx_ready (up_rx_ready_01), - .up_tx_pll_rst (up_tx_pll_rst_01), - .up_tx_pll_locked (up_tx_pll_locked_01), - .up_tx_rst (up_tx_rst_01), - .up_tx_user_ready (up_tx_user_ready_01), - .up_tx_rst_done (up_tx_rst_done_01), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_01), - .up_tx_rate (up_tx_rate_01), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_01), - .up_tx_out_clk_sel (up_tx_out_clk_sel_01), - .up_tx_sel (up_tx_sel_01), - .up_tx_enb (up_tx_enb_01), - .up_tx_addr (up_tx_addr_01), - .up_tx_wr (up_tx_wr_01), - .up_tx_wdata (up_tx_wdata_01), - .up_tx_rdata (up_tx_rdata_01), - .up_tx_ready (up_tx_ready_01)); + .up_es_sel (up_es_sel_1), + .up_es_enb (up_es_enb_1), + .up_es_addr (up_es_addr_1), + .up_es_wr (up_es_wr_1), + .up_es_wdata (up_es_wdata_1), + .up_es_rdata (up_es_rdata_1), + .up_es_ready (up_es_ready_1), + .up_rx_pll_rst (up_rx_pll_rst_1), + .up_rx_pll_locked (up_rx_pll_locked_1), + .up_rx_rst (up_rx_rst_1), + .up_rx_user_ready (up_rx_user_ready_1), + .up_rx_rst_done (up_rx_rst_done_1), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1), + .up_rx_rate (up_rx_rate_1), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_1), + .up_rx_out_clk_sel (up_rx_out_clk_sel_1), + .up_rx_sel (up_rx_sel_1), + .up_rx_enb (up_rx_enb_1), + .up_rx_addr (up_rx_addr_1), + .up_rx_wr (up_rx_wr_1), + .up_rx_wdata (up_rx_wdata_1), + .up_rx_rdata (up_rx_rdata_1), + .up_rx_ready (up_rx_ready_1), + .up_tx_pll_rst (up_tx_pll_rst_1), + .up_tx_pll_locked (up_tx_pll_locked_1), + .up_tx_rst (up_tx_rst_1), + .up_tx_user_ready (up_tx_user_ready_1), + .up_tx_rst_done (up_tx_rst_done_1), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1), + .up_tx_rate (up_tx_rate_1), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_1), + .up_tx_out_clk_sel (up_tx_out_clk_sel_1), + .up_tx_sel (up_tx_sel_1), + .up_tx_enb (up_tx_enb_1), + .up_tx_addr (up_tx_addr_1), + .up_tx_wr (up_tx_wr_1), + .up_tx_wdata (up_tx_wdata_1), + .up_tx_rdata (up_tx_rdata_1), + .up_tx_ready (up_tx_ready_1)); + end else begin + assign rx_out_clk_1 = 1'd0; + assign rx_charisk_1 = 4'd0; + assign rx_disperr_1 = 4'd0; + assign rx_notintable_1 = 4'd0; + assign rx_data_1 = 32'd0; + assign tx_1_p = 1'd0; + assign tx_1_n = 1'd0; + assign tx_out_clk_1 = 1'd0; + assign up_es_rdata_1 = 16'd0; + assign up_es_ready_1 = 1'd0; + assign up_rx_pll_locked_1 = 1'd0; + assign up_rx_rst_done_1 = 1'd0; + assign up_rx_rdata_1 = 16'd0; + assign up_rx_ready_1 = 1'd0; + assign up_tx_pll_locked_1 = 1'd0; + assign up_tx_rst_done_1 = 1'd0; + assign up_tx_rdata_1 = 16'd0; + assign up_tx_ready_1 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 3) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (2), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1265,74 +1316,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_02 ( - .qpll2ch_clk (qpll2ch_clk_00), - .qpll2ch_ref_clk (qpll2ch_ref_clk_00), - .qpll2ch_locked (qpll2ch_locked_00), - .cpll_ref_clk (cpll_ref_clk_02), - .rx_p (rx_02_p), - .rx_n (rx_02_n), - .rx_out_clk (rx_out_clk_02), - .rx_clk (rx_clk_02), - .rx_charisk (rx_charisk_02), - .rx_disperr (rx_disperr_02), - .rx_notintable (rx_notintable_02), - .rx_data (rx_data_02), - .rx_calign (rx_calign_02), - .tx_p (tx_02_p), - .tx_n (tx_02_n), - .tx_out_clk (tx_out_clk_02), - .tx_clk (tx_clk_02), - .tx_charisk (tx_charisk_02), - .tx_data (tx_data_02), + i_xch_2 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_2), + .rx_p (rx_2_p), + .rx_n (rx_2_n), + .rx_out_clk (rx_out_clk_2), + .rx_clk (rx_clk_2), + .rx_charisk (rx_charisk_2), + .rx_disperr (rx_disperr_2), + .rx_notintable (rx_notintable_2), + .rx_data (rx_data_2), + .rx_calign (rx_calign_2), + .tx_p (tx_2_p), + .tx_n (tx_2_n), + .tx_out_clk (tx_out_clk_2), + .tx_clk (tx_clk_2), + .tx_charisk (tx_charisk_2), + .tx_data (tx_data_2), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_02), - .up_es_enb (up_es_enb_02), - .up_es_addr (up_es_addr_02), - .up_es_wr (up_es_wr_02), - .up_es_wdata (up_es_wdata_02), - .up_es_rdata (up_es_rdata_02), - .up_es_ready (up_es_ready_02), - .up_rx_pll_rst (up_rx_pll_rst_02), - .up_rx_pll_locked (up_rx_pll_locked_02), - .up_rx_rst (up_rx_rst_02), - .up_rx_user_ready (up_rx_user_ready_02), - .up_rx_rst_done (up_rx_rst_done_02), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_02), - .up_rx_rate (up_rx_rate_02), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_02), - .up_rx_out_clk_sel (up_rx_out_clk_sel_02), - .up_rx_sel (up_rx_sel_02), - .up_rx_enb (up_rx_enb_02), - .up_rx_addr (up_rx_addr_02), - .up_rx_wr (up_rx_wr_02), - .up_rx_wdata (up_rx_wdata_02), - .up_rx_rdata (up_rx_rdata_02), - .up_rx_ready (up_rx_ready_02), - .up_tx_pll_rst (up_tx_pll_rst_02), - .up_tx_pll_locked (up_tx_pll_locked_02), - .up_tx_rst (up_tx_rst_02), - .up_tx_user_ready (up_tx_user_ready_02), - .up_tx_rst_done (up_tx_rst_done_02), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_02), - .up_tx_rate (up_tx_rate_02), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_02), - .up_tx_out_clk_sel (up_tx_out_clk_sel_02), - .up_tx_sel (up_tx_sel_02), - .up_tx_enb (up_tx_enb_02), - .up_tx_addr (up_tx_addr_02), - .up_tx_wr (up_tx_wr_02), - .up_tx_wdata (up_tx_wdata_02), - .up_tx_rdata (up_tx_rdata_02), - .up_tx_ready (up_tx_ready_02)); + .up_es_sel (up_es_sel_2), + .up_es_enb (up_es_enb_2), + .up_es_addr (up_es_addr_2), + .up_es_wr (up_es_wr_2), + .up_es_wdata (up_es_wdata_2), + .up_es_rdata (up_es_rdata_2), + .up_es_ready (up_es_ready_2), + .up_rx_pll_rst (up_rx_pll_rst_2), + .up_rx_pll_locked (up_rx_pll_locked_2), + .up_rx_rst (up_rx_rst_2), + .up_rx_user_ready (up_rx_user_ready_2), + .up_rx_rst_done (up_rx_rst_done_2), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2), + .up_rx_rate (up_rx_rate_2), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_2), + .up_rx_out_clk_sel (up_rx_out_clk_sel_2), + .up_rx_sel (up_rx_sel_2), + .up_rx_enb (up_rx_enb_2), + .up_rx_addr (up_rx_addr_2), + .up_rx_wr (up_rx_wr_2), + .up_rx_wdata (up_rx_wdata_2), + .up_rx_rdata (up_rx_rdata_2), + .up_rx_ready (up_rx_ready_2), + .up_tx_pll_rst (up_tx_pll_rst_2), + .up_tx_pll_locked (up_tx_pll_locked_2), + .up_tx_rst (up_tx_rst_2), + .up_tx_user_ready (up_tx_user_ready_2), + .up_tx_rst_done (up_tx_rst_done_2), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2), + .up_tx_rate (up_tx_rate_2), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_2), + .up_tx_out_clk_sel (up_tx_out_clk_sel_2), + .up_tx_sel (up_tx_sel_2), + .up_tx_enb (up_tx_enb_2), + .up_tx_addr (up_tx_addr_2), + .up_tx_wr (up_tx_wr_2), + .up_tx_wdata (up_tx_wdata_2), + .up_tx_rdata (up_tx_rdata_2), + .up_tx_ready (up_tx_ready_2)); + end else begin + assign rx_out_clk_2 = 1'd0; + assign rx_charisk_2 = 4'd0; + assign rx_disperr_2 = 4'd0; + assign rx_notintable_2 = 4'd0; + assign rx_data_2 = 32'd0; + assign tx_2_p = 1'd0; + assign tx_2_n = 1'd0; + assign tx_out_clk_2 = 1'd0; + assign up_es_rdata_2 = 16'd0; + assign up_es_ready_2 = 1'd0; + assign up_rx_pll_locked_2 = 1'd0; + assign up_rx_rst_done_2 = 1'd0; + assign up_rx_rdata_2 = 16'd0; + assign up_rx_ready_2 = 1'd0; + assign up_tx_pll_locked_2 = 1'd0; + assign up_tx_rst_done_2 = 1'd0; + assign up_tx_rdata_2 = 16'd0; + assign up_tx_ready_2 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 4) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (3), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1344,101 +1415,126 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_03 ( - .qpll2ch_clk (qpll2ch_clk_00), - .qpll2ch_ref_clk (qpll2ch_ref_clk_00), - .qpll2ch_locked (qpll2ch_locked_00), - .cpll_ref_clk (cpll_ref_clk_03), - .rx_p (rx_03_p), - .rx_n (rx_03_n), - .rx_out_clk (rx_out_clk_03), - .rx_clk (rx_clk_03), - .rx_charisk (rx_charisk_03), - .rx_disperr (rx_disperr_03), - .rx_notintable (rx_notintable_03), - .rx_data (rx_data_03), - .rx_calign (rx_calign_03), - .tx_p (tx_03_p), - .tx_n (tx_03_n), - .tx_out_clk (tx_out_clk_03), - .tx_clk (tx_clk_03), - .tx_charisk (tx_charisk_03), - .tx_data (tx_data_03), + i_xch_3 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_3), + .rx_p (rx_3_p), + .rx_n (rx_3_n), + .rx_out_clk (rx_out_clk_3), + .rx_clk (rx_clk_3), + .rx_charisk (rx_charisk_3), + .rx_disperr (rx_disperr_3), + .rx_notintable (rx_notintable_3), + .rx_data (rx_data_3), + .rx_calign (rx_calign_3), + .tx_p (tx_3_p), + .tx_n (tx_3_n), + .tx_out_clk (tx_out_clk_3), + .tx_clk (tx_clk_3), + .tx_charisk (tx_charisk_3), + .tx_data (tx_data_3), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_03), - .up_es_enb (up_es_enb_03), - .up_es_addr (up_es_addr_03), - .up_es_wr (up_es_wr_03), - .up_es_wdata (up_es_wdata_03), - .up_es_rdata (up_es_rdata_03), - .up_es_ready (up_es_ready_03), - .up_rx_pll_rst (up_rx_pll_rst_03), - .up_rx_pll_locked (up_rx_pll_locked_03), - .up_rx_rst (up_rx_rst_03), - .up_rx_user_ready (up_rx_user_ready_03), - .up_rx_rst_done (up_rx_rst_done_03), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_03), - .up_rx_rate (up_rx_rate_03), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_03), - .up_rx_out_clk_sel (up_rx_out_clk_sel_03), - .up_rx_sel (up_rx_sel_03), - .up_rx_enb (up_rx_enb_03), - .up_rx_addr (up_rx_addr_03), - .up_rx_wr (up_rx_wr_03), - .up_rx_wdata (up_rx_wdata_03), - .up_rx_rdata (up_rx_rdata_03), - .up_rx_ready (up_rx_ready_03), - .up_tx_pll_rst (up_tx_pll_rst_03), - .up_tx_pll_locked (up_tx_pll_locked_03), - .up_tx_rst (up_tx_rst_03), - .up_tx_user_ready (up_tx_user_ready_03), - .up_tx_rst_done (up_tx_rst_done_03), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_03), - .up_tx_rate (up_tx_rate_03), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_03), - .up_tx_out_clk_sel (up_tx_out_clk_sel_03), - .up_tx_sel (up_tx_sel_03), - .up_tx_enb (up_tx_enb_03), - .up_tx_addr (up_tx_addr_03), - .up_tx_wr (up_tx_wr_03), - .up_tx_wdata (up_tx_wdata_03), - .up_tx_rdata (up_tx_rdata_03), - .up_tx_ready (up_tx_ready_03)); + .up_es_sel (up_es_sel_3), + .up_es_enb (up_es_enb_3), + .up_es_addr (up_es_addr_3), + .up_es_wr (up_es_wr_3), + .up_es_wdata (up_es_wdata_3), + .up_es_rdata (up_es_rdata_3), + .up_es_ready (up_es_ready_3), + .up_rx_pll_rst (up_rx_pll_rst_3), + .up_rx_pll_locked (up_rx_pll_locked_3), + .up_rx_rst (up_rx_rst_3), + .up_rx_user_ready (up_rx_user_ready_3), + .up_rx_rst_done (up_rx_rst_done_3), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3), + .up_rx_rate (up_rx_rate_3), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_3), + .up_rx_out_clk_sel (up_rx_out_clk_sel_3), + .up_rx_sel (up_rx_sel_3), + .up_rx_enb (up_rx_enb_3), + .up_rx_addr (up_rx_addr_3), + .up_rx_wr (up_rx_wr_3), + .up_rx_wdata (up_rx_wdata_3), + .up_rx_rdata (up_rx_rdata_3), + .up_rx_ready (up_rx_ready_3), + .up_tx_pll_rst (up_tx_pll_rst_3), + .up_tx_pll_locked (up_tx_pll_locked_3), + .up_tx_rst (up_tx_rst_3), + .up_tx_user_ready (up_tx_user_ready_3), + .up_tx_rst_done (up_tx_rst_done_3), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3), + .up_tx_rate (up_tx_rate_3), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_3), + .up_tx_out_clk_sel (up_tx_out_clk_sel_3), + .up_tx_sel (up_tx_sel_3), + .up_tx_enb (up_tx_enb_3), + .up_tx_addr (up_tx_addr_3), + .up_tx_wr (up_tx_wr_3), + .up_tx_wdata (up_tx_wdata_3), + .up_tx_rdata (up_tx_rdata_3), + .up_tx_ready (up_tx_ready_3)); + end else begin + assign rx_out_clk_3 = 1'd0; + assign rx_charisk_3 = 4'd0; + assign rx_disperr_3 = 4'd0; + assign rx_notintable_3 = 4'd0; + assign rx_data_3 = 32'd0; + assign tx_3_p = 1'd0; + assign tx_3_n = 1'd0; + assign tx_out_clk_3 = 1'd0; + assign up_es_rdata_3 = 16'd0; + assign up_es_ready_3 = 1'd0; + assign up_rx_pll_locked_3 = 1'd0; + assign up_rx_rst_done_3 = 1'd0; + assign up_rx_rdata_3 = 16'd0; + assign up_rx_ready_3 = 1'd0; + assign up_tx_pll_locked_3 = 1'd0; + assign up_tx_rst_done_3 = 1'd0; + assign up_tx_rdata_3 = 16'd0; + assign up_tx_ready_3 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 5) begin util_adxcvr_xcm #( - .XCVR_ID (n), + .XCVR_ID (4), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) - i_xcm_04 ( - .qpll_ref_clk (qpll_ref_clk_04), - .qpll2ch_clk (qpll2ch_clk_04), - .qpll2ch_ref_clk (qpll2ch_ref_clk_04), - .qpll2ch_locked (qpll2ch_locked_04), + i_xcm_4 ( + .qpll_ref_clk (qpll_ref_clk_4), + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), .up_rstn (up_rstn), .up_clk (up_clk), - .up_qpll_rst (up_qpll_rst_04), - .up_cm_sel (up_cm_sel_04), - .up_cm_enb (up_cm_enb_04), - .up_cm_addr (up_cm_addr_04), - .up_cm_wr (up_cm_wr_04), - .up_cm_wdata (up_cm_wdata_04), - .up_cm_rdata (up_cm_rdata_04), - .up_cm_ready (up_cm_ready_04)); + .up_qpll_rst (up_qpll_rst_4), + .up_cm_sel (up_cm_sel_4), + .up_cm_enb (up_cm_enb_4), + .up_cm_addr (up_cm_addr_4), + .up_cm_wr (up_cm_wr_4), + .up_cm_wdata (up_cm_wdata_4), + .up_cm_rdata (up_cm_rdata_4), + .up_cm_ready (up_cm_ready_4)); + end else begin + assign qpll2ch_clk_4 = 1'd0; + assign qpll2ch_ref_clk_4 = 1'd0; + assign qpll2ch_locked_4 = 1'd0; + assign up_cm_rdata_4 = 16'd0; + assign up_cm_ready_4 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 5) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (4), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1450,74 +1546,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_04 ( - .qpll2ch_clk (qpll2ch_clk_04), - .qpll2ch_ref_clk (qpll2ch_ref_clk_04), - .qpll2ch_locked (qpll2ch_locked_04), - .cpll_ref_clk (cpll_ref_clk_04), - .rx_p (rx_04_p), - .rx_n (rx_04_n), - .rx_out_clk (rx_out_clk_04), - .rx_clk (rx_clk_04), - .rx_charisk (rx_charisk_04), - .rx_disperr (rx_disperr_04), - .rx_notintable (rx_notintable_04), - .rx_data (rx_data_04), - .rx_calign (rx_calign_04), - .tx_p (tx_04_p), - .tx_n (tx_04_n), - .tx_out_clk (tx_out_clk_04), - .tx_clk (tx_clk_04), - .tx_charisk (tx_charisk_04), - .tx_data (tx_data_04), + i_xch_4 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_4), + .rx_p (rx_4_p), + .rx_n (rx_4_n), + .rx_out_clk (rx_out_clk_4), + .rx_clk (rx_clk_4), + .rx_charisk (rx_charisk_4), + .rx_disperr (rx_disperr_4), + .rx_notintable (rx_notintable_4), + .rx_data (rx_data_4), + .rx_calign (rx_calign_4), + .tx_p (tx_4_p), + .tx_n (tx_4_n), + .tx_out_clk (tx_out_clk_4), + .tx_clk (tx_clk_4), + .tx_charisk (tx_charisk_4), + .tx_data (tx_data_4), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_04), - .up_es_enb (up_es_enb_04), - .up_es_addr (up_es_addr_04), - .up_es_wr (up_es_wr_04), - .up_es_wdata (up_es_wdata_04), - .up_es_rdata (up_es_rdata_04), - .up_es_ready (up_es_ready_04), - .up_rx_pll_rst (up_rx_pll_rst_04), - .up_rx_pll_locked (up_rx_pll_locked_04), - .up_rx_rst (up_rx_rst_04), - .up_rx_user_ready (up_rx_user_ready_04), - .up_rx_rst_done (up_rx_rst_done_04), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_04), - .up_rx_rate (up_rx_rate_04), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_04), - .up_rx_out_clk_sel (up_rx_out_clk_sel_04), - .up_rx_sel (up_rx_sel_04), - .up_rx_enb (up_rx_enb_04), - .up_rx_addr (up_rx_addr_04), - .up_rx_wr (up_rx_wr_04), - .up_rx_wdata (up_rx_wdata_04), - .up_rx_rdata (up_rx_rdata_04), - .up_rx_ready (up_rx_ready_04), - .up_tx_pll_rst (up_tx_pll_rst_04), - .up_tx_pll_locked (up_tx_pll_locked_04), - .up_tx_rst (up_tx_rst_04), - .up_tx_user_ready (up_tx_user_ready_04), - .up_tx_rst_done (up_tx_rst_done_04), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_04), - .up_tx_rate (up_tx_rate_04), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_04), - .up_tx_out_clk_sel (up_tx_out_clk_sel_04), - .up_tx_sel (up_tx_sel_04), - .up_tx_enb (up_tx_enb_04), - .up_tx_addr (up_tx_addr_04), - .up_tx_wr (up_tx_wr_04), - .up_tx_wdata (up_tx_wdata_04), - .up_tx_rdata (up_tx_rdata_04), - .up_tx_ready (up_tx_ready_04)); + .up_es_sel (up_es_sel_4), + .up_es_enb (up_es_enb_4), + .up_es_addr (up_es_addr_4), + .up_es_wr (up_es_wr_4), + .up_es_wdata (up_es_wdata_4), + .up_es_rdata (up_es_rdata_4), + .up_es_ready (up_es_ready_4), + .up_rx_pll_rst (up_rx_pll_rst_4), + .up_rx_pll_locked (up_rx_pll_locked_4), + .up_rx_rst (up_rx_rst_4), + .up_rx_user_ready (up_rx_user_ready_4), + .up_rx_rst_done (up_rx_rst_done_4), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4), + .up_rx_rate (up_rx_rate_4), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_4), + .up_rx_out_clk_sel (up_rx_out_clk_sel_4), + .up_rx_sel (up_rx_sel_4), + .up_rx_enb (up_rx_enb_4), + .up_rx_addr (up_rx_addr_4), + .up_rx_wr (up_rx_wr_4), + .up_rx_wdata (up_rx_wdata_4), + .up_rx_rdata (up_rx_rdata_4), + .up_rx_ready (up_rx_ready_4), + .up_tx_pll_rst (up_tx_pll_rst_4), + .up_tx_pll_locked (up_tx_pll_locked_4), + .up_tx_rst (up_tx_rst_4), + .up_tx_user_ready (up_tx_user_ready_4), + .up_tx_rst_done (up_tx_rst_done_4), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4), + .up_tx_rate (up_tx_rate_4), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_4), + .up_tx_out_clk_sel (up_tx_out_clk_sel_4), + .up_tx_sel (up_tx_sel_4), + .up_tx_enb (up_tx_enb_4), + .up_tx_addr (up_tx_addr_4), + .up_tx_wr (up_tx_wr_4), + .up_tx_wdata (up_tx_wdata_4), + .up_tx_rdata (up_tx_rdata_4), + .up_tx_ready (up_tx_ready_4)); + end else begin + assign rx_out_clk_4 = 1'd0; + assign rx_charisk_4 = 4'd0; + assign rx_disperr_4 = 4'd0; + assign rx_notintable_4 = 4'd0; + assign rx_data_4 = 32'd0; + assign tx_4_p = 1'd0; + assign tx_4_n = 1'd0; + assign tx_out_clk_4 = 1'd0; + assign up_es_rdata_4 = 16'd0; + assign up_es_ready_4 = 1'd0; + assign up_rx_pll_locked_4 = 1'd0; + assign up_rx_rst_done_4 = 1'd0; + assign up_rx_rdata_4 = 16'd0; + assign up_rx_ready_4 = 1'd0; + assign up_tx_pll_locked_4 = 1'd0; + assign up_tx_rst_done_4 = 1'd0; + assign up_tx_rdata_4 = 16'd0; + assign up_tx_ready_4 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 6) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (5), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1529,74 +1645,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_05 ( - .qpll2ch_clk (qpll2ch_clk_04), - .qpll2ch_ref_clk (qpll2ch_ref_clk_04), - .qpll2ch_locked (qpll2ch_locked_04), - .cpll_ref_clk (cpll_ref_clk_05), - .rx_p (rx_05_p), - .rx_n (rx_05_n), - .rx_out_clk (rx_out_clk_05), - .rx_clk (rx_clk_05), - .rx_charisk (rx_charisk_05), - .rx_disperr (rx_disperr_05), - .rx_notintable (rx_notintable_05), - .rx_data (rx_data_05), - .rx_calign (rx_calign_05), - .tx_p (tx_05_p), - .tx_n (tx_05_n), - .tx_out_clk (tx_out_clk_05), - .tx_clk (tx_clk_05), - .tx_charisk (tx_charisk_05), - .tx_data (tx_data_05), + i_xch_5 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_5), + .rx_p (rx_5_p), + .rx_n (rx_5_n), + .rx_out_clk (rx_out_clk_5), + .rx_clk (rx_clk_5), + .rx_charisk (rx_charisk_5), + .rx_disperr (rx_disperr_5), + .rx_notintable (rx_notintable_5), + .rx_data (rx_data_5), + .rx_calign (rx_calign_5), + .tx_p (tx_5_p), + .tx_n (tx_5_n), + .tx_out_clk (tx_out_clk_5), + .tx_clk (tx_clk_5), + .tx_charisk (tx_charisk_5), + .tx_data (tx_data_5), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_05), - .up_es_enb (up_es_enb_05), - .up_es_addr (up_es_addr_05), - .up_es_wr (up_es_wr_05), - .up_es_wdata (up_es_wdata_05), - .up_es_rdata (up_es_rdata_05), - .up_es_ready (up_es_ready_05), - .up_rx_pll_rst (up_rx_pll_rst_05), - .up_rx_pll_locked (up_rx_pll_locked_05), - .up_rx_rst (up_rx_rst_05), - .up_rx_user_ready (up_rx_user_ready_05), - .up_rx_rst_done (up_rx_rst_done_05), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_05), - .up_rx_rate (up_rx_rate_05), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_05), - .up_rx_out_clk_sel (up_rx_out_clk_sel_05), - .up_rx_sel (up_rx_sel_05), - .up_rx_enb (up_rx_enb_05), - .up_rx_addr (up_rx_addr_05), - .up_rx_wr (up_rx_wr_05), - .up_rx_wdata (up_rx_wdata_05), - .up_rx_rdata (up_rx_rdata_05), - .up_rx_ready (up_rx_ready_05), - .up_tx_pll_rst (up_tx_pll_rst_05), - .up_tx_pll_locked (up_tx_pll_locked_05), - .up_tx_rst (up_tx_rst_05), - .up_tx_user_ready (up_tx_user_ready_05), - .up_tx_rst_done (up_tx_rst_done_05), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_05), - .up_tx_rate (up_tx_rate_05), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_05), - .up_tx_out_clk_sel (up_tx_out_clk_sel_05), - .up_tx_sel (up_tx_sel_05), - .up_tx_enb (up_tx_enb_05), - .up_tx_addr (up_tx_addr_05), - .up_tx_wr (up_tx_wr_05), - .up_tx_wdata (up_tx_wdata_05), - .up_tx_rdata (up_tx_rdata_05), - .up_tx_ready (up_tx_ready_05)); + .up_es_sel (up_es_sel_5), + .up_es_enb (up_es_enb_5), + .up_es_addr (up_es_addr_5), + .up_es_wr (up_es_wr_5), + .up_es_wdata (up_es_wdata_5), + .up_es_rdata (up_es_rdata_5), + .up_es_ready (up_es_ready_5), + .up_rx_pll_rst (up_rx_pll_rst_5), + .up_rx_pll_locked (up_rx_pll_locked_5), + .up_rx_rst (up_rx_rst_5), + .up_rx_user_ready (up_rx_user_ready_5), + .up_rx_rst_done (up_rx_rst_done_5), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5), + .up_rx_rate (up_rx_rate_5), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_5), + .up_rx_out_clk_sel (up_rx_out_clk_sel_5), + .up_rx_sel (up_rx_sel_5), + .up_rx_enb (up_rx_enb_5), + .up_rx_addr (up_rx_addr_5), + .up_rx_wr (up_rx_wr_5), + .up_rx_wdata (up_rx_wdata_5), + .up_rx_rdata (up_rx_rdata_5), + .up_rx_ready (up_rx_ready_5), + .up_tx_pll_rst (up_tx_pll_rst_5), + .up_tx_pll_locked (up_tx_pll_locked_5), + .up_tx_rst (up_tx_rst_5), + .up_tx_user_ready (up_tx_user_ready_5), + .up_tx_rst_done (up_tx_rst_done_5), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5), + .up_tx_rate (up_tx_rate_5), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_5), + .up_tx_out_clk_sel (up_tx_out_clk_sel_5), + .up_tx_sel (up_tx_sel_5), + .up_tx_enb (up_tx_enb_5), + .up_tx_addr (up_tx_addr_5), + .up_tx_wr (up_tx_wr_5), + .up_tx_wdata (up_tx_wdata_5), + .up_tx_rdata (up_tx_rdata_5), + .up_tx_ready (up_tx_ready_5)); + end else begin + assign rx_out_clk_5 = 1'd0; + assign rx_charisk_5 = 4'd0; + assign rx_disperr_5 = 4'd0; + assign rx_notintable_5 = 4'd0; + assign rx_data_5 = 32'd0; + assign tx_5_p = 1'd0; + assign tx_5_n = 1'd0; + assign tx_out_clk_5 = 1'd0; + assign up_es_rdata_5 = 16'd0; + assign up_es_ready_5 = 1'd0; + assign up_rx_pll_locked_5 = 1'd0; + assign up_rx_rst_done_5 = 1'd0; + assign up_rx_rdata_5 = 16'd0; + assign up_rx_ready_5 = 1'd0; + assign up_tx_pll_locked_5 = 1'd0; + assign up_tx_rst_done_5 = 1'd0; + assign up_tx_rdata_5 = 16'd0; + assign up_tx_ready_5 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 7) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (6), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1608,74 +1744,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_06 ( - .qpll2ch_clk (qpll2ch_clk_04), - .qpll2ch_ref_clk (qpll2ch_ref_clk_04), - .qpll2ch_locked (qpll2ch_locked_04), - .cpll_ref_clk (cpll_ref_clk_06), - .rx_p (rx_06_p), - .rx_n (rx_06_n), - .rx_out_clk (rx_out_clk_06), - .rx_clk (rx_clk_06), - .rx_charisk (rx_charisk_06), - .rx_disperr (rx_disperr_06), - .rx_notintable (rx_notintable_06), - .rx_data (rx_data_06), - .rx_calign (rx_calign_06), - .tx_p (tx_06_p), - .tx_n (tx_06_n), - .tx_out_clk (tx_out_clk_06), - .tx_clk (tx_clk_06), - .tx_charisk (tx_charisk_06), - .tx_data (tx_data_06), + i_xch_6 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_6), + .rx_p (rx_6_p), + .rx_n (rx_6_n), + .rx_out_clk (rx_out_clk_6), + .rx_clk (rx_clk_6), + .rx_charisk (rx_charisk_6), + .rx_disperr (rx_disperr_6), + .rx_notintable (rx_notintable_6), + .rx_data (rx_data_6), + .rx_calign (rx_calign_6), + .tx_p (tx_6_p), + .tx_n (tx_6_n), + .tx_out_clk (tx_out_clk_6), + .tx_clk (tx_clk_6), + .tx_charisk (tx_charisk_6), + .tx_data (tx_data_6), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_06), - .up_es_enb (up_es_enb_06), - .up_es_addr (up_es_addr_06), - .up_es_wr (up_es_wr_06), - .up_es_wdata (up_es_wdata_06), - .up_es_rdata (up_es_rdata_06), - .up_es_ready (up_es_ready_06), - .up_rx_pll_rst (up_rx_pll_rst_06), - .up_rx_pll_locked (up_rx_pll_locked_06), - .up_rx_rst (up_rx_rst_06), - .up_rx_user_ready (up_rx_user_ready_06), - .up_rx_rst_done (up_rx_rst_done_06), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_06), - .up_rx_rate (up_rx_rate_06), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_06), - .up_rx_out_clk_sel (up_rx_out_clk_sel_06), - .up_rx_sel (up_rx_sel_06), - .up_rx_enb (up_rx_enb_06), - .up_rx_addr (up_rx_addr_06), - .up_rx_wr (up_rx_wr_06), - .up_rx_wdata (up_rx_wdata_06), - .up_rx_rdata (up_rx_rdata_06), - .up_rx_ready (up_rx_ready_06), - .up_tx_pll_rst (up_tx_pll_rst_06), - .up_tx_pll_locked (up_tx_pll_locked_06), - .up_tx_rst (up_tx_rst_06), - .up_tx_user_ready (up_tx_user_ready_06), - .up_tx_rst_done (up_tx_rst_done_06), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_06), - .up_tx_rate (up_tx_rate_06), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_06), - .up_tx_out_clk_sel (up_tx_out_clk_sel_06), - .up_tx_sel (up_tx_sel_06), - .up_tx_enb (up_tx_enb_06), - .up_tx_addr (up_tx_addr_06), - .up_tx_wr (up_tx_wr_06), - .up_tx_wdata (up_tx_wdata_06), - .up_tx_rdata (up_tx_rdata_06), - .up_tx_ready (up_tx_ready_06)); + .up_es_sel (up_es_sel_6), + .up_es_enb (up_es_enb_6), + .up_es_addr (up_es_addr_6), + .up_es_wr (up_es_wr_6), + .up_es_wdata (up_es_wdata_6), + .up_es_rdata (up_es_rdata_6), + .up_es_ready (up_es_ready_6), + .up_rx_pll_rst (up_rx_pll_rst_6), + .up_rx_pll_locked (up_rx_pll_locked_6), + .up_rx_rst (up_rx_rst_6), + .up_rx_user_ready (up_rx_user_ready_6), + .up_rx_rst_done (up_rx_rst_done_6), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6), + .up_rx_rate (up_rx_rate_6), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_6), + .up_rx_out_clk_sel (up_rx_out_clk_sel_6), + .up_rx_sel (up_rx_sel_6), + .up_rx_enb (up_rx_enb_6), + .up_rx_addr (up_rx_addr_6), + .up_rx_wr (up_rx_wr_6), + .up_rx_wdata (up_rx_wdata_6), + .up_rx_rdata (up_rx_rdata_6), + .up_rx_ready (up_rx_ready_6), + .up_tx_pll_rst (up_tx_pll_rst_6), + .up_tx_pll_locked (up_tx_pll_locked_6), + .up_tx_rst (up_tx_rst_6), + .up_tx_user_ready (up_tx_user_ready_6), + .up_tx_rst_done (up_tx_rst_done_6), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6), + .up_tx_rate (up_tx_rate_6), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_6), + .up_tx_out_clk_sel (up_tx_out_clk_sel_6), + .up_tx_sel (up_tx_sel_6), + .up_tx_enb (up_tx_enb_6), + .up_tx_addr (up_tx_addr_6), + .up_tx_wr (up_tx_wr_6), + .up_tx_wdata (up_tx_wdata_6), + .up_tx_rdata (up_tx_rdata_6), + .up_tx_ready (up_tx_ready_6)); + end else begin + assign rx_out_clk_6 = 1'd0; + assign rx_charisk_6 = 4'd0; + assign rx_disperr_6 = 4'd0; + assign rx_notintable_6 = 4'd0; + assign rx_data_6 = 32'd0; + assign tx_6_p = 1'd0; + assign tx_6_n = 1'd0; + assign tx_out_clk_6 = 1'd0; + assign up_es_rdata_6 = 16'd0; + assign up_es_ready_6 = 1'd0; + assign up_rx_pll_locked_6 = 1'd0; + assign up_rx_rst_done_6 = 1'd0; + assign up_rx_rdata_6 = 16'd0; + assign up_rx_ready_6 = 1'd0; + assign up_tx_pll_locked_6 = 1'd0; + assign up_tx_rst_done_6 = 1'd0; + assign up_tx_rdata_6 = 16'd0; + assign up_tx_ready_6 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 8) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (7), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1687,101 +1843,126 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_07 ( - .qpll2ch_clk (qpll2ch_clk_04), - .qpll2ch_ref_clk (qpll2ch_ref_clk_04), - .qpll2ch_locked (qpll2ch_locked_04), - .cpll_ref_clk (cpll_ref_clk_07), - .rx_p (rx_07_p), - .rx_n (rx_07_n), - .rx_out_clk (rx_out_clk_07), - .rx_clk (rx_clk_07), - .rx_charisk (rx_charisk_07), - .rx_disperr (rx_disperr_07), - .rx_notintable (rx_notintable_07), - .rx_data (rx_data_07), - .rx_calign (rx_calign_07), - .tx_p (tx_07_p), - .tx_n (tx_07_n), - .tx_out_clk (tx_out_clk_07), - .tx_clk (tx_clk_07), - .tx_charisk (tx_charisk_07), - .tx_data (tx_data_07), + i_xch_7 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_7), + .rx_p (rx_7_p), + .rx_n (rx_7_n), + .rx_out_clk (rx_out_clk_7), + .rx_clk (rx_clk_7), + .rx_charisk (rx_charisk_7), + .rx_disperr (rx_disperr_7), + .rx_notintable (rx_notintable_7), + .rx_data (rx_data_7), + .rx_calign (rx_calign_7), + .tx_p (tx_7_p), + .tx_n (tx_7_n), + .tx_out_clk (tx_out_clk_7), + .tx_clk (tx_clk_7), + .tx_charisk (tx_charisk_7), + .tx_data (tx_data_7), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_07), - .up_es_enb (up_es_enb_07), - .up_es_addr (up_es_addr_07), - .up_es_wr (up_es_wr_07), - .up_es_wdata (up_es_wdata_07), - .up_es_rdata (up_es_rdata_07), - .up_es_ready (up_es_ready_07), - .up_rx_pll_rst (up_rx_pll_rst_07), - .up_rx_pll_locked (up_rx_pll_locked_07), - .up_rx_rst (up_rx_rst_07), - .up_rx_user_ready (up_rx_user_ready_07), - .up_rx_rst_done (up_rx_rst_done_07), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_07), - .up_rx_rate (up_rx_rate_07), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_07), - .up_rx_out_clk_sel (up_rx_out_clk_sel_07), - .up_rx_sel (up_rx_sel_07), - .up_rx_enb (up_rx_enb_07), - .up_rx_addr (up_rx_addr_07), - .up_rx_wr (up_rx_wr_07), - .up_rx_wdata (up_rx_wdata_07), - .up_rx_rdata (up_rx_rdata_07), - .up_rx_ready (up_rx_ready_07), - .up_tx_pll_rst (up_tx_pll_rst_07), - .up_tx_pll_locked (up_tx_pll_locked_07), - .up_tx_rst (up_tx_rst_07), - .up_tx_user_ready (up_tx_user_ready_07), - .up_tx_rst_done (up_tx_rst_done_07), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_07), - .up_tx_rate (up_tx_rate_07), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_07), - .up_tx_out_clk_sel (up_tx_out_clk_sel_07), - .up_tx_sel (up_tx_sel_07), - .up_tx_enb (up_tx_enb_07), - .up_tx_addr (up_tx_addr_07), - .up_tx_wr (up_tx_wr_07), - .up_tx_wdata (up_tx_wdata_07), - .up_tx_rdata (up_tx_rdata_07), - .up_tx_ready (up_tx_ready_07)); + .up_es_sel (up_es_sel_7), + .up_es_enb (up_es_enb_7), + .up_es_addr (up_es_addr_7), + .up_es_wr (up_es_wr_7), + .up_es_wdata (up_es_wdata_7), + .up_es_rdata (up_es_rdata_7), + .up_es_ready (up_es_ready_7), + .up_rx_pll_rst (up_rx_pll_rst_7), + .up_rx_pll_locked (up_rx_pll_locked_7), + .up_rx_rst (up_rx_rst_7), + .up_rx_user_ready (up_rx_user_ready_7), + .up_rx_rst_done (up_rx_rst_done_7), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7), + .up_rx_rate (up_rx_rate_7), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_7), + .up_rx_out_clk_sel (up_rx_out_clk_sel_7), + .up_rx_sel (up_rx_sel_7), + .up_rx_enb (up_rx_enb_7), + .up_rx_addr (up_rx_addr_7), + .up_rx_wr (up_rx_wr_7), + .up_rx_wdata (up_rx_wdata_7), + .up_rx_rdata (up_rx_rdata_7), + .up_rx_ready (up_rx_ready_7), + .up_tx_pll_rst (up_tx_pll_rst_7), + .up_tx_pll_locked (up_tx_pll_locked_7), + .up_tx_rst (up_tx_rst_7), + .up_tx_user_ready (up_tx_user_ready_7), + .up_tx_rst_done (up_tx_rst_done_7), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7), + .up_tx_rate (up_tx_rate_7), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_7), + .up_tx_out_clk_sel (up_tx_out_clk_sel_7), + .up_tx_sel (up_tx_sel_7), + .up_tx_enb (up_tx_enb_7), + .up_tx_addr (up_tx_addr_7), + .up_tx_wr (up_tx_wr_7), + .up_tx_wdata (up_tx_wdata_7), + .up_tx_rdata (up_tx_rdata_7), + .up_tx_ready (up_tx_ready_7)); + end else begin + assign rx_out_clk_7 = 1'd0; + assign rx_charisk_7 = 4'd0; + assign rx_disperr_7 = 4'd0; + assign rx_notintable_7 = 4'd0; + assign rx_data_7 = 32'd0; + assign tx_7_p = 1'd0; + assign tx_7_n = 1'd0; + assign tx_out_clk_7 = 1'd0; + assign up_es_rdata_7 = 16'd0; + assign up_es_ready_7 = 1'd0; + assign up_rx_pll_locked_7 = 1'd0; + assign up_rx_rst_done_7 = 1'd0; + assign up_rx_rdata_7 = 16'd0; + assign up_rx_ready_7 = 1'd0; + assign up_tx_pll_locked_7 = 1'd0; + assign up_tx_rst_done_7 = 1'd0; + assign up_tx_rdata_7 = 16'd0; + assign up_tx_ready_7 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 9) begin util_adxcvr_xcm #( - .XCVR_ID (n), + .XCVR_ID (8), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV)) - i_xcm_08 ( - .qpll_ref_clk (qpll_ref_clk_08), - .qpll2ch_clk (qpll2ch_clk_08), - .qpll2ch_ref_clk (qpll2ch_ref_clk_08), - .qpll2ch_locked (qpll2ch_locked_08), + i_xcm_8 ( + .qpll_ref_clk (qpll_ref_clk_8), + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), .up_rstn (up_rstn), .up_clk (up_clk), - .up_qpll_rst (up_qpll_rst_08), - .up_cm_sel (up_cm_sel_08), - .up_cm_enb (up_cm_enb_08), - .up_cm_addr (up_cm_addr_08), - .up_cm_wr (up_cm_wr_08), - .up_cm_wdata (up_cm_wdata_08), - .up_cm_rdata (up_cm_rdata_08), - .up_cm_ready (up_cm_ready_08)); + .up_qpll_rst (up_qpll_rst_8), + .up_cm_sel (up_cm_sel_8), + .up_cm_enb (up_cm_enb_8), + .up_cm_addr (up_cm_addr_8), + .up_cm_wr (up_cm_wr_8), + .up_cm_wdata (up_cm_wdata_8), + .up_cm_rdata (up_cm_rdata_8), + .up_cm_ready (up_cm_ready_8)); + end else begin + assign qpll2ch_clk_8 = 1'd0; + assign qpll2ch_ref_clk_8 = 1'd0; + assign qpll2ch_locked_8 = 1'd0; + assign up_cm_rdata_8 = 16'd0; + assign up_cm_ready_8 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 9) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (8), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1793,74 +1974,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_08 ( - .qpll2ch_clk (qpll2ch_clk_08), - .qpll2ch_ref_clk (qpll2ch_ref_clk_08), - .qpll2ch_locked (qpll2ch_locked_08), - .cpll_ref_clk (cpll_ref_clk_08), - .rx_p (rx_08_p), - .rx_n (rx_08_n), - .rx_out_clk (rx_out_clk_08), - .rx_clk (rx_clk_08), - .rx_charisk (rx_charisk_08), - .rx_disperr (rx_disperr_08), - .rx_notintable (rx_notintable_08), - .rx_data (rx_data_08), - .rx_calign (rx_calign_08), - .tx_p (tx_08_p), - .tx_n (tx_08_n), - .tx_out_clk (tx_out_clk_08), - .tx_clk (tx_clk_08), - .tx_charisk (tx_charisk_08), - .tx_data (tx_data_08), + i_xch_8 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_8), + .rx_p (rx_8_p), + .rx_n (rx_8_n), + .rx_out_clk (rx_out_clk_8), + .rx_clk (rx_clk_8), + .rx_charisk (rx_charisk_8), + .rx_disperr (rx_disperr_8), + .rx_notintable (rx_notintable_8), + .rx_data (rx_data_8), + .rx_calign (rx_calign_8), + .tx_p (tx_8_p), + .tx_n (tx_8_n), + .tx_out_clk (tx_out_clk_8), + .tx_clk (tx_clk_8), + .tx_charisk (tx_charisk_8), + .tx_data (tx_data_8), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_08), - .up_es_enb (up_es_enb_08), - .up_es_addr (up_es_addr_08), - .up_es_wr (up_es_wr_08), - .up_es_wdata (up_es_wdata_08), - .up_es_rdata (up_es_rdata_08), - .up_es_ready (up_es_ready_08), - .up_rx_pll_rst (up_rx_pll_rst_08), - .up_rx_pll_locked (up_rx_pll_locked_08), - .up_rx_rst (up_rx_rst_08), - .up_rx_user_ready (up_rx_user_ready_08), - .up_rx_rst_done (up_rx_rst_done_08), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_08), - .up_rx_rate (up_rx_rate_08), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_08), - .up_rx_out_clk_sel (up_rx_out_clk_sel_08), - .up_rx_sel (up_rx_sel_08), - .up_rx_enb (up_rx_enb_08), - .up_rx_addr (up_rx_addr_08), - .up_rx_wr (up_rx_wr_08), - .up_rx_wdata (up_rx_wdata_08), - .up_rx_rdata (up_rx_rdata_08), - .up_rx_ready (up_rx_ready_08), - .up_tx_pll_rst (up_tx_pll_rst_08), - .up_tx_pll_locked (up_tx_pll_locked_08), - .up_tx_rst (up_tx_rst_08), - .up_tx_user_ready (up_tx_user_ready_08), - .up_tx_rst_done (up_tx_rst_done_08), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_08), - .up_tx_rate (up_tx_rate_08), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_08), - .up_tx_out_clk_sel (up_tx_out_clk_sel_08), - .up_tx_sel (up_tx_sel_08), - .up_tx_enb (up_tx_enb_08), - .up_tx_addr (up_tx_addr_08), - .up_tx_wr (up_tx_wr_08), - .up_tx_wdata (up_tx_wdata_08), - .up_tx_rdata (up_tx_rdata_08), - .up_tx_ready (up_tx_ready_08)); + .up_es_sel (up_es_sel_8), + .up_es_enb (up_es_enb_8), + .up_es_addr (up_es_addr_8), + .up_es_wr (up_es_wr_8), + .up_es_wdata (up_es_wdata_8), + .up_es_rdata (up_es_rdata_8), + .up_es_ready (up_es_ready_8), + .up_rx_pll_rst (up_rx_pll_rst_8), + .up_rx_pll_locked (up_rx_pll_locked_8), + .up_rx_rst (up_rx_rst_8), + .up_rx_user_ready (up_rx_user_ready_8), + .up_rx_rst_done (up_rx_rst_done_8), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8), + .up_rx_rate (up_rx_rate_8), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_8), + .up_rx_out_clk_sel (up_rx_out_clk_sel_8), + .up_rx_sel (up_rx_sel_8), + .up_rx_enb (up_rx_enb_8), + .up_rx_addr (up_rx_addr_8), + .up_rx_wr (up_rx_wr_8), + .up_rx_wdata (up_rx_wdata_8), + .up_rx_rdata (up_rx_rdata_8), + .up_rx_ready (up_rx_ready_8), + .up_tx_pll_rst (up_tx_pll_rst_8), + .up_tx_pll_locked (up_tx_pll_locked_8), + .up_tx_rst (up_tx_rst_8), + .up_tx_user_ready (up_tx_user_ready_8), + .up_tx_rst_done (up_tx_rst_done_8), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8), + .up_tx_rate (up_tx_rate_8), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_8), + .up_tx_out_clk_sel (up_tx_out_clk_sel_8), + .up_tx_sel (up_tx_sel_8), + .up_tx_enb (up_tx_enb_8), + .up_tx_addr (up_tx_addr_8), + .up_tx_wr (up_tx_wr_8), + .up_tx_wdata (up_tx_wdata_8), + .up_tx_rdata (up_tx_rdata_8), + .up_tx_ready (up_tx_ready_8)); + end else begin + assign rx_out_clk_8 = 1'd0; + assign rx_charisk_8 = 4'd0; + assign rx_disperr_8 = 4'd0; + assign rx_notintable_8 = 4'd0; + assign rx_data_8 = 32'd0; + assign tx_8_p = 1'd0; + assign tx_8_n = 1'd0; + assign tx_out_clk_8 = 1'd0; + assign up_es_rdata_8 = 16'd0; + assign up_es_ready_8 = 1'd0; + assign up_rx_pll_locked_8 = 1'd0; + assign up_rx_rst_done_8 = 1'd0; + assign up_rx_rdata_8 = 16'd0; + assign up_rx_ready_8 = 1'd0; + assign up_tx_pll_locked_8 = 1'd0; + assign up_tx_rst_done_8 = 1'd0; + assign up_tx_rdata_8 = 16'd0; + assign up_tx_ready_8 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 10) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (9), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1872,74 +2073,94 @@ module util_adxcvr ( .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE), .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) - i_xch_09 ( - .qpll2ch_clk (qpll2ch_clk_08), - .qpll2ch_ref_clk (qpll2ch_ref_clk_08), - .qpll2ch_locked (qpll2ch_locked_08), - .cpll_ref_clk (cpll_ref_clk_09), - .rx_p (rx_09_p), - .rx_n (rx_09_n), - .rx_out_clk (rx_out_clk_09), - .rx_clk (rx_clk_09), - .rx_charisk (rx_charisk_09), - .rx_disperr (rx_disperr_09), - .rx_notintable (rx_notintable_09), - .rx_data (rx_data_09), - .rx_calign (rx_calign_09), - .tx_p (tx_09_p), - .tx_n (tx_09_n), - .tx_out_clk (tx_out_clk_09), - .tx_clk (tx_clk_09), - .tx_charisk (tx_charisk_09), - .tx_data (tx_data_09), + i_xch_9 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_9), + .rx_p (rx_9_p), + .rx_n (rx_9_n), + .rx_out_clk (rx_out_clk_9), + .rx_clk (rx_clk_9), + .rx_charisk (rx_charisk_9), + .rx_disperr (rx_disperr_9), + .rx_notintable (rx_notintable_9), + .rx_data (rx_data_9), + .rx_calign (rx_calign_9), + .tx_p (tx_9_p), + .tx_n (tx_9_n), + .tx_out_clk (tx_out_clk_9), + .tx_clk (tx_clk_9), + .tx_charisk (tx_charisk_9), + .tx_data (tx_data_9), .up_rstn (up_rstn), .up_clk (up_clk), - .up_es_sel (up_es_sel_09), - .up_es_enb (up_es_enb_09), - .up_es_addr (up_es_addr_09), - .up_es_wr (up_es_wr_09), - .up_es_wdata (up_es_wdata_09), - .up_es_rdata (up_es_rdata_09), - .up_es_ready (up_es_ready_09), - .up_rx_pll_rst (up_rx_pll_rst_09), - .up_rx_pll_locked (up_rx_pll_locked_09), - .up_rx_rst (up_rx_rst_09), - .up_rx_user_ready (up_rx_user_ready_09), - .up_rx_rst_done (up_rx_rst_done_09), - .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_09), - .up_rx_rate (up_rx_rate_09), - .up_rx_sys_clk_sel (up_rx_sys_clk_sel_09), - .up_rx_out_clk_sel (up_rx_out_clk_sel_09), - .up_rx_sel (up_rx_sel_09), - .up_rx_enb (up_rx_enb_09), - .up_rx_addr (up_rx_addr_09), - .up_rx_wr (up_rx_wr_09), - .up_rx_wdata (up_rx_wdata_09), - .up_rx_rdata (up_rx_rdata_09), - .up_rx_ready (up_rx_ready_09), - .up_tx_pll_rst (up_tx_pll_rst_09), - .up_tx_pll_locked (up_tx_pll_locked_09), - .up_tx_rst (up_tx_rst_09), - .up_tx_user_ready (up_tx_user_ready_09), - .up_tx_rst_done (up_tx_rst_done_09), - .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_09), - .up_tx_rate (up_tx_rate_09), - .up_tx_sys_clk_sel (up_tx_sys_clk_sel_09), - .up_tx_out_clk_sel (up_tx_out_clk_sel_09), - .up_tx_sel (up_tx_sel_09), - .up_tx_enb (up_tx_enb_09), - .up_tx_addr (up_tx_addr_09), - .up_tx_wr (up_tx_wr_09), - .up_tx_wdata (up_tx_wdata_09), - .up_tx_rdata (up_tx_rdata_09), - .up_tx_ready (up_tx_ready_09)); + .up_es_sel (up_es_sel_9), + .up_es_enb (up_es_enb_9), + .up_es_addr (up_es_addr_9), + .up_es_wr (up_es_wr_9), + .up_es_wdata (up_es_wdata_9), + .up_es_rdata (up_es_rdata_9), + .up_es_ready (up_es_ready_9), + .up_rx_pll_rst (up_rx_pll_rst_9), + .up_rx_pll_locked (up_rx_pll_locked_9), + .up_rx_rst (up_rx_rst_9), + .up_rx_user_ready (up_rx_user_ready_9), + .up_rx_rst_done (up_rx_rst_done_9), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9), + .up_rx_rate (up_rx_rate_9), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_9), + .up_rx_out_clk_sel (up_rx_out_clk_sel_9), + .up_rx_sel (up_rx_sel_9), + .up_rx_enb (up_rx_enb_9), + .up_rx_addr (up_rx_addr_9), + .up_rx_wr (up_rx_wr_9), + .up_rx_wdata (up_rx_wdata_9), + .up_rx_rdata (up_rx_rdata_9), + .up_rx_ready (up_rx_ready_9), + .up_tx_pll_rst (up_tx_pll_rst_9), + .up_tx_pll_locked (up_tx_pll_locked_9), + .up_tx_rst (up_tx_rst_9), + .up_tx_user_ready (up_tx_user_ready_9), + .up_tx_rst_done (up_tx_rst_done_9), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9), + .up_tx_rate (up_tx_rate_9), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_9), + .up_tx_out_clk_sel (up_tx_out_clk_sel_9), + .up_tx_sel (up_tx_sel_9), + .up_tx_enb (up_tx_enb_9), + .up_tx_addr (up_tx_addr_9), + .up_tx_wr (up_tx_wr_9), + .up_tx_wdata (up_tx_wdata_9), + .up_tx_rdata (up_tx_rdata_9), + .up_tx_ready (up_tx_ready_9)); + end else begin + assign rx_out_clk_9 = 1'd0; + assign rx_charisk_9 = 4'd0; + assign rx_disperr_9 = 4'd0; + assign rx_notintable_9 = 4'd0; + assign rx_data_9 = 32'd0; + assign tx_9_p = 1'd0; + assign tx_9_n = 1'd0; + assign tx_out_clk_9 = 1'd0; + assign up_es_rdata_9 = 16'd0; + assign up_es_ready_9 = 1'd0; + assign up_rx_pll_locked_9 = 1'd0; + assign up_rx_rst_done_9 = 1'd0; + assign up_rx_rdata_9 = 16'd0; + assign up_rx_ready_9 = 1'd0; + assign up_tx_pll_locked_9 = 1'd0; + assign up_tx_rst_done_9 = 1'd0; + assign up_tx_rdata_9 = 16'd0; + assign up_tx_ready_9 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 11) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (10), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -1952,9 +2173,9 @@ module util_adxcvr ( .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_10 ( - .qpll2ch_clk (qpll2ch_clk_08), - .qpll2ch_ref_clk (qpll2ch_ref_clk_08), - .qpll2ch_locked (qpll2ch_locked_08), + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), .cpll_ref_clk (cpll_ref_clk_10), .rx_p (rx_10_p), .rx_n (rx_10_n), @@ -2012,13 +2233,33 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_10), .up_tx_rdata (up_tx_rdata_10), .up_tx_ready (up_tx_ready_10)); + end else begin + assign rx_out_clk_10 = 1'd0; + assign rx_charisk_10 = 4'd0; + assign rx_disperr_10 = 4'd0; + assign rx_notintable_10 = 4'd0; + assign rx_data_10 = 32'd0; + assign tx_10_p = 1'd0; + assign tx_10_n = 1'd0; + assign tx_out_clk_10 = 1'd0; + assign up_es_rdata_10 = 16'd0; + assign up_es_ready_10 = 1'd0; + assign up_rx_pll_locked_10 = 1'd0; + assign up_rx_rst_done_10 = 1'd0; + assign up_rx_rdata_10 = 16'd0; + assign up_rx_ready_10 = 1'd0; + assign up_tx_pll_locked_10 = 1'd0; + assign up_tx_rst_done_10 = 1'd0; + assign up_tx_rdata_10 = 16'd0; + assign up_tx_ready_10 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 12) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (11), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -2031,9 +2272,9 @@ module util_adxcvr ( .PMA_RSV (PMA_RSV), .RX_CDR_CFG (RX_CDR_CFG)) i_xch_11 ( - .qpll2ch_clk (qpll2ch_clk_08), - .qpll2ch_ref_clk (qpll2ch_ref_clk_08), - .qpll2ch_locked (qpll2ch_locked_08), + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), .cpll_ref_clk (cpll_ref_clk_11), .rx_p (rx_11_p), .rx_n (rx_11_n), @@ -2091,13 +2332,32 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_11), .up_tx_rdata (up_tx_rdata_11), .up_tx_ready (up_tx_ready_11)); + end else begin + assign rx_out_clk_11 = 1'd0; + assign rx_charisk_11 = 4'd0; + assign rx_disperr_11 = 4'd0; + assign rx_notintable_11 = 4'd0; + assign rx_data_11 = 32'd0; + assign tx_11_p = 1'd0; + assign tx_11_n = 1'd0; + assign tx_out_clk_11 = 1'd0; + assign up_es_rdata_11 = 16'd0; + assign up_es_ready_11 = 1'd0; + assign up_rx_pll_locked_11 = 1'd0; + assign up_rx_rst_done_11 = 1'd0; + assign up_rx_rdata_11 = 16'd0; + assign up_rx_ready_11 = 1'd0; + assign up_tx_pll_locked_11 = 1'd0; + assign up_tx_rst_done_11 = 1'd0; + assign up_tx_rdata_11 = 16'd0; + assign up_tx_ready_11 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 13) begin util_adxcvr_xcm #( - .XCVR_ID (n), + .XCVR_ID (12), .GTH_OR_GTX_N (GTH_OR_GTX_N), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), @@ -2118,13 +2378,19 @@ module util_adxcvr ( .up_cm_wdata (up_cm_wdata_12), .up_cm_rdata (up_cm_rdata_12), .up_cm_ready (up_cm_ready_12)); + end else begin + assign qpll2ch_clk_12 = 1'd0; + assign qpll2ch_ref_clk_12 = 1'd0; + assign qpll2ch_locked_12 = 1'd0; + assign up_cm_rdata_12 = 16'd0; + assign up_cm_ready_12 = 1'd0; end endgenerate generate if (NUM_OF_LANES >= 13) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (12), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -2197,13 +2463,33 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_12), .up_tx_rdata (up_tx_rdata_12), .up_tx_ready (up_tx_ready_12)); + end else begin + assign rx_out_clk_12 = 1'd0; + assign rx_charisk_12 = 4'd0; + assign rx_disperr_12 = 4'd0; + assign rx_notintable_12 = 4'd0; + assign rx_data_12 = 32'd0; + assign tx_12_p = 1'd0; + assign tx_12_n = 1'd0; + assign tx_out_clk_12 = 1'd0; + assign up_es_rdata_12 = 16'd0; + assign up_es_ready_12 = 1'd0; + assign up_rx_pll_locked_12 = 1'd0; + assign up_rx_rst_done_12 = 1'd0; + assign up_rx_rdata_12 = 16'd0; + assign up_rx_ready_12 = 1'd0; + assign up_tx_pll_locked_12 = 1'd0; + assign up_tx_rst_done_12 = 1'd0; + assign up_tx_rdata_12 = 16'd0; + assign up_tx_ready_12 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 14) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (13), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -2276,13 +2562,33 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_13), .up_tx_rdata (up_tx_rdata_13), .up_tx_ready (up_tx_ready_13)); + end else begin + assign rx_out_clk_13 = 1'd0; + assign rx_charisk_13 = 4'd0; + assign rx_disperr_13 = 4'd0; + assign rx_notintable_13 = 4'd0; + assign rx_data_13 = 32'd0; + assign tx_13_p = 1'd0; + assign tx_13_n = 1'd0; + assign tx_out_clk_13 = 1'd0; + assign up_es_rdata_13 = 16'd0; + assign up_es_ready_13 = 1'd0; + assign up_rx_pll_locked_13 = 1'd0; + assign up_rx_rst_done_13 = 1'd0; + assign up_rx_rdata_13 = 16'd0; + assign up_rx_ready_13 = 1'd0; + assign up_tx_pll_locked_13 = 1'd0; + assign up_tx_rst_done_13 = 1'd0; + assign up_tx_rdata_13 = 16'd0; + assign up_tx_ready_13 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 15) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (14), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -2355,13 +2661,33 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_14), .up_tx_rdata (up_tx_rdata_14), .up_tx_ready (up_tx_ready_14)); + end else begin + assign rx_out_clk_14 = 1'd0; + assign rx_charisk_14 = 4'd0; + assign rx_disperr_14 = 4'd0; + assign rx_notintable_14 = 4'd0; + assign rx_data_14 = 32'd0; + assign tx_14_p = 1'd0; + assign tx_14_n = 1'd0; + assign tx_out_clk_14 = 1'd0; + assign up_es_rdata_14 = 16'd0; + assign up_es_ready_14 = 1'd0; + assign up_rx_pll_locked_14 = 1'd0; + assign up_rx_rst_done_14 = 1'd0; + assign up_rx_rdata_14 = 16'd0; + assign up_rx_ready_14 = 1'd0; + assign up_tx_pll_locked_14 = 1'd0; + assign up_tx_rst_done_14 = 1'd0; + assign up_tx_rdata_14 = 16'd0; + assign up_tx_ready_14 = 1'd0; end endgenerate + generate if (NUM_OF_LANES >= 16) begin util_adxcvr_xch #( - .XCVR_ID (n), + .XCVR_ID (15), .GTH_OR_GTX_N (GTH_OR_GTX_N), .CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N), .CPLL_FBDIV (CPLL_FBDIV), @@ -2434,10 +2760,29 @@ module util_adxcvr ( .up_tx_wdata (up_tx_wdata_15), .up_tx_rdata (up_tx_rdata_15), .up_tx_ready (up_tx_ready_15)); + end else begin + assign rx_out_clk_15 = 1'd0; + assign rx_charisk_15 = 4'd0; + assign rx_disperr_15 = 4'd0; + assign rx_notintable_15 = 4'd0; + assign rx_data_15 = 32'd0; + assign tx_15_p = 1'd0; + assign tx_15_n = 1'd0; + assign tx_out_clk_15 = 1'd0; + assign up_es_rdata_15 = 16'd0; + assign up_es_ready_15 = 1'd0; + assign up_rx_pll_locked_15 = 1'd0; + assign up_rx_rst_done_15 = 1'd0; + assign up_rx_rdata_15 = 16'd0; + assign up_rx_ready_15 = 1'd0; + assign up_tx_pll_locked_15 = 1'd0; + assign up_tx_rst_done_15 = 1'd0; + assign up_tx_rdata_15 = 16'd0; + assign up_tx_ready_15 = 1'd0; end endgenerate -endmodule +endmodule // *************************************************************************** // *************************************************************************** diff --git a/library/util_adxcvr/util_adxcvr_ip.tcl b/library/util_adxcvr/util_adxcvr_ip.tcl index 03b1b119f..0162c5f78 100644 --- a/library/util_adxcvr/util_adxcvr_ip.tcl +++ b/library/util_adxcvr/util_adxcvr_ip.tcl @@ -1,16 +1,615 @@ -# ip +## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_adxcvr adi_ip_files util_adxcvr [list \ - "util_adxcvr_intf.svh" \ - "util_adxcvr_xcm.sv" \ - "util_adxcvr_xch.sv" \ - "util_adxcvr.sv" ] + "util_adxcvr_xcm.v" \ + "util_adxcvr_xch.v" \ + "util_adxcvr.v" ] adi_ip_properties_lite util_adxcvr +ipx::remove_all_bus_interface [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +for {set n 0} {$n < 16} {incr n} { + + if {($n%4) == 0} { + adi_if_infer_bus ADI:user:if_xcvr_cm slave up_cm_${n} [list \ + "sel up_cm_sel_${n} "\ + "enb up_cm_enb_${n} "\ + "addr up_cm_addr_${n} "\ + "wr up_cm_wr_${n} "\ + "wdata up_cm_wdata_${n} "\ + "rdata up_cm_rdata_${n} "\ + "ready up_cm_ready_${n} "] + } + + adi_if_infer_bus ADI:user:if_xcvr_cm slave up_es_${n} [list \ + "sel up_es_sel_${n} "\ + "enb up_es_enb_${n} "\ + "addr up_es_addr_${n} "\ + "wr up_es_wr_${n} "\ + "wdata up_es_wdata_${n} "\ + "rdata up_es_rdata_${n} "\ + "ready up_es_ready_${n} "] + + adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \ + "pll_rst up_rx_pll_rst_${n} "\ + "pll_locked up_rx_pll_locked_${n} "\ + "rst up_rx_rst_${n} "\ + "user_ready up_rx_user_ready_${n} "\ + "rst_done up_rx_rst_done_${n} "\ + "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ + "rate up_rx_rate_${n} "\ + "sys_clk_sel up_rx_sys_clk_sel_${n} "\ + "out_clk_sel up_rx_out_clk_sel_${n} "\ + "sel up_rx_sel_${n} "\ + "enb up_rx_enb_${n} "\ + "addr up_rx_addr_${n} "\ + "wr up_rx_wr_${n} "\ + "wdata up_rx_wdata_${n} "\ + "rdata up_rx_rdata_${n} "\ + "ready up_rx_ready_${n} "] + + adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \ + "pll_rst up_tx_pll_rst_${n} "\ + "pll_locked up_tx_pll_locked_${n} "\ + "rst up_tx_rst_${n} "\ + "user_ready up_tx_user_ready_${n} "\ + "rst_done up_tx_rst_done_${n} "\ + "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ + "rate up_tx_rate_${n} "\ + "sys_clk_sel up_tx_sys_clk_sel_${n} "\ + "out_clk_sel up_tx_out_clk_sel_${n} "\ + "sel up_tx_sel_${n} "\ + "enb up_tx_enb_${n} "\ + "addr up_tx_addr_${n} "\ + "wr up_tx_wr_${n} "\ + "wdata up_tx_wdata_${n} "\ + "rdata up_tx_rdata_${n} "\ + "ready up_tx_ready_${n} "] + + ipx::add_bus_interface rx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + + ipx::add_bus_interface tx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + +} + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports rx_*0* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0))} \ + [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \ + [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0))} \ + [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports rx_*1* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1))} \ + [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports rx_*2* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2))} \ + [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports rx_*3* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3))} \ + [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports rx_*4* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4))} \ + [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \ + [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4))} \ + [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports rx_*5* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5))} \ + [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports rx_*6* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6))} \ + [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports rx_*7* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7))} \ + [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports rx_*8* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8))} \ + [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \ + [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8))} \ + [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports rx_*9* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9))} \ + [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports rx_*10* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10))} \ + [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports rx_*11* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11))} \ + [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports rx_*12* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12))} \ + [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \ + [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12))} \ + [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports rx_*13* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13))} \ + [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports rx_*14* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14))} \ + [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports rx_*15* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15)) or \ + ((spirit:decode(id('MODELPARAM_VALUE.CPLL_TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15))} \ + [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] + ipx::save_core [ipx::current_core] diff --git a/library/util_adxcvr/util_adxcvr_xch.v b/library/util_adxcvr/util_adxcvr_xch.v index 2734e04e4..0b19f9d6a 100644 --- a/library/util_adxcvr/util_adxcvr_xch.v +++ b/library/util_adxcvr/util_adxcvr_xch.v @@ -39,68 +39,85 @@ module util_adxcvr_xch ( - // rst and clocks + // pll interface - input ref_clk, - input pll_rst, - - input qpll_clk, - input qpll_ref_clk, - input qpll_locked, + input qpll2ch_clk, + input qpll2ch_ref_clk, + input qpll2ch_locked, + input cpll_ref_clk, // receive input rx_p, input rx_n, - input rx_rst, - input rx_clk, - input rx_lpm_dfe_n, - input [ 2:0] rx_rate, - input [ 1:0] rx_sys_clk_sel, - input [ 2:0] rx_out_clk_sel, output rx_out_clk, - output rx_rst_done, - output rx_pll_locked, - input rx_user_ready, - output [ 3:0] rx_gt_charisk, - output [ 3:0] rx_gt_disperr, - output [ 3:0] rx_gt_notintable, - output [31:0] rx_gt_data, - input rx_gt_calign, + input rx_clk, + output [ 3:0] rx_charisk, + output [ 3:0] rx_disperr, + output [ 3:0] rx_notintable, + output [31:0] rx_data, + input rx_calign, // transmit output tx_p, output tx_n, - input tx_rst, - input tx_clk, - input [ 2:0] tx_rate, - input [ 1:0] tx_sys_clk_sel, - input [ 2:0] tx_out_clk_sel, output tx_out_clk, - output tx_rst_done, - output tx_pll_locked, - input tx_user_ready, - input [ 3:0] tx_gt_charisk, - input [31:0] tx_gt_data, + input tx_clk, + input [ 3:0] tx_charisk, + input [31:0] tx_data, - // drp interface + // up interface input up_rstn, input up_clk, - input [ 7:0] up_drp_sel, - input up_drp_enb, - input [11:0] up_drp_addr, - input up_drp_wr, - input [15:0] up_drp_wdata, - output [15:0] up_drp_rdata, - output up_drp_ready); + input [ 7:0] up_es_sel, + input up_es_enb, + input [11:0] up_es_addr, + input up_es_wr, + input [15:0] up_es_wdata, + output [15:0] up_es_rdata, + output up_es_ready, + input up_rx_pll_rst, + output up_rx_pll_locked, + input up_rx_rst, + input up_rx_user_ready, + output up_rx_rst_done, + input up_rx_lpm_dfe_n, + input [ 2:0] up_rx_rate, + input [ 1:0] up_rx_sys_clk_sel, + input [ 2:0] up_rx_out_clk_sel, + input [ 7:0] up_rx_sel, + input up_rx_enb, + input [11:0] up_rx_addr, + input up_rx_wr, + input [15:0] up_rx_wdata, + output [15:0] up_rx_rdata, + output up_rx_ready, + input up_tx_pll_rst, + output up_tx_pll_locked, + input up_tx_rst, + input up_tx_user_ready, + output up_tx_rst_done, + input up_tx_lpm_dfe_n, + input [ 2:0] up_tx_rate, + input [ 1:0] up_tx_sys_clk_sel, + input [ 2:0] up_tx_out_clk_sel, + input [ 7:0] up_tx_sel, + input up_tx_enb, + input [11:0] up_tx_addr, + input up_tx_wr, + input [15:0] up_tx_wdata, + output [15:0] up_tx_rdata, + output up_tx_ready); // parameters + parameter integer XCVR_ID = 0; parameter integer GTH_OR_GTX_N = 0; + parameter integer CPLL_TX_OR_RX_N = 0; parameter integer CPLL_FBDIV = 2; parameter integer RX_OUT_DIV = 1; parameter integer RX_CLK25_DIV = 10; @@ -113,60 +130,127 @@ module util_adxcvr_xch ( // internal registers - reg up_drp_enb_int = 'd0; - reg [11:0] up_drp_addr_int = 'd0; - reg up_drp_wr_int = 'd0; - reg [15:0] up_drp_wdata_int = 'd0; - reg [15:0] up_drp_rdata_int = 'd0; - reg up_drp_ready_int = 'd0; + reg [15:0] up_es_rdata_int = 'd0; + reg up_es_ready_int = 'd0; + reg [15:0] up_rx_rdata_int = 'd0; + reg up_rx_ready_int = 'd0; + reg [15:0] up_tx_rdata_int = 'd0; + reg up_tx_ready_int = 'd0; + reg [ 2:0] up_sel_int = 'd0; + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; // internal signals - wire [ 3:0] rx_charisk_open_s; - wire [ 3:0] rx_disperr_open_s; - wire [ 3:0] rx_notintable_open_s; - wire [31:0] rx_data_open_s; + wire up_cpll_rst; + wire up_es_enb_s; + wire up_rx_enb_s; + wire up_tx_enb_s; + wire [15:0] up_rdata_s; + wire up_ready_s; wire [ 1:0] rx_sys_clk_sel_s; wire [ 1:0] tx_sys_clk_sel_s; wire [ 1:0] rx_pll_clk_sel_s; wire [ 1:0] tx_pll_clk_sel_s; + wire [ 3:0] rx_charisk_open_s; + wire [ 3:0] rx_disperr_open_s; + wire [ 3:0] rx_notintable_open_s; + wire [31:0] rx_data_open_s; wire cpll_locked_s; - wire [15:0] up_drp_rdata_s; - wire up_drp_ready_s; - // pll locked + // pll - assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s; - assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s; + assign up_cpll_rst = (CPLL_TX_OR_RX_N == 1) ? up_tx_pll_rst : up_rx_pll_rst; + assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; + assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; // drp access - assign up_drp_rdata = up_drp_rdata_int; - assign up_drp_ready = up_drp_ready_int; + assign up_es_rdata = up_es_rdata_int; + assign up_es_ready = up_es_ready_int; + assign up_rx_rdata = up_rx_rdata_int; + assign up_rx_ready = up_rx_ready_int; + assign up_tx_rdata = up_tx_rdata_int; + assign up_tx_ready = up_tx_ready_int; - always @(posedge up_clk or negedge up_rstn) begin + assign up_es_enb_s = ((up_es_sel == XCVR_ID) || + (up_es_sel == 8'hff)) ? up_es_enb : 1'b0; + + assign up_rx_enb_s = ((up_rx_sel == XCVR_ID) || + (up_rx_sel == 8'hff)) ? up_rx_enb : 1'b0; + + assign up_tx_enb_s = ((up_tx_sel == XCVR_ID) || + (up_tx_sel == 8'hff)) ? up_tx_enb : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin - up_drp_enb_int <= 1'd0; - up_drp_addr_int <= 12'd0; - up_drp_wr_int <= 1'd0; - up_drp_wdata_int <= 15'd0; - up_drp_rdata_int <= 15'd0; - up_drp_ready_int <= 1'd0; + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + up_sel_int <= 3'd0; + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; end else begin - if ((up_drp_sel == XCVR_ID) || (up_drp_sel == 8'hff)) begin - up_drp_enb_int <= up_drp_enb; - up_drp_addr_int <= up_drp_addr; - up_drp_wr_int <= up_drp_wr; - up_drp_wdata_int <= up_drp_wdata; - up_drp_rdata_int <= up_drp_rdata_s; - up_drp_ready_int <= up_drp_ready_s; + if (up_sel_int == 3'b100) begin + up_es_rdata_int <= up_rdata_s; + up_es_ready_int <= up_ready_s; end else begin - up_drp_enb_int <= 1'd0; - up_drp_addr_int <= 12'd0; - up_drp_wr_int <= 1'd0; - up_drp_wdata_int <= 15'd0; - up_drp_rdata_int <= 15'd0; - up_drp_ready_int <= 1'd0; + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + end + if (up_sel_int == 3'b101) begin + up_rx_rdata_int <= up_rdata_s; + up_rx_ready_int <= up_ready_s; + end else begin + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + end + if (up_sel_int == 3'b110) begin + up_tx_rdata_int <= up_rdata_s; + up_tx_ready_int <= up_ready_s; + end else begin + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + end + if (up_sel_int[2] == 1'b1) begin + if (up_ready_s == 1'b1) begin + up_sel_int <= 3'b000; + end + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end else if (up_es_enb_s == 1'b1) begin + up_sel_int <= 3'b100; + up_enb_int <= 1'b1; + up_addr_int <= up_es_addr; + up_wr_int <= up_es_wr; + up_wdata_int <= up_es_wdata; + end else if (up_rx_enb_s == 1'b1) begin + up_sel_int <= 3'b101; + up_enb_int <= 1'b1; + up_addr_int <= up_rx_addr; + up_wr_int <= up_rx_wr; + up_wdata_int <= up_rx_wdata; + end else if (up_tx_enb_s == 1'b1) begin + up_sel_int <= 3'b110; + up_enb_int <= 1'b1; + up_addr_int <= up_tx_addr; + up_wr_int <= up_tx_wr; + up_wdata_int <= up_tx_wdata; + end else begin + up_sel_int <= 3'b000; + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; end end end @@ -175,8 +259,8 @@ module util_adxcvr_xch ( generate if (GTH_OR_GTX_N == 0) begin - assign rx_sys_clk_sel_s = rx_sys_clk_sel; - assign tx_sys_clk_sel_s = tx_sys_clk_sel; + assign rx_sys_clk_sel_s = up_rx_sys_clk_sel; + assign tx_sys_clk_sel_s = up_tx_sys_clk_sel; assign rx_pll_clk_sel_s = 2'd0; assign tx_pll_clk_sel_s = 2'd0; end @@ -392,7 +476,7 @@ module util_adxcvr_xch ( .CPLLPD (1'b0), .CPLLREFCLKLOST (), .CPLLREFCLKSEL (3'b001), - .CPLLRESET (pll_rst), + .CPLLRESET (up_cpll_rst), .GTRSVD (16'b0000000000000000), .PCSRSVDIN (16'b0000000000000000), .PCSRSVDIN2 (5'b00000), @@ -404,33 +488,33 @@ module util_adxcvr_xch ( .GTGREFCLK (1'd0), .GTNORTHREFCLK0 (1'd0), .GTNORTHREFCLK1 (1'd0), - .GTREFCLK0 (ref_clk), + .GTREFCLK0 (cpll_ref_clk), .GTREFCLK1 (1'd0), .GTSOUTHREFCLK0 (1'd0), .GTSOUTHREFCLK1 (1'd0), - .DRPADDR (up_drp_addr_int[8:0]), + .DRPADDR (up_addr_int[8:0]), .DRPCLK (up_clk), - .DRPDI (up_drp_wdata_int), - .DRPDO (up_drp_rdata_s), - .DRPEN (up_drp_enb_int), - .DRPRDY (up_drp_ready_s), - .DRPWE (up_drp_wr_int), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), .GTREFCLKMONITOR (), - .QPLLCLK (qpll_clk), - .QPLLREFCLK (qpll_ref_clk), + .QPLLCLK (qpll2ch_clk), + .QPLLREFCLK (qpll2ch_ref_clk), .RXSYSCLKSEL (rx_sys_clk_sel_s), .TXSYSCLKSEL (tx_sys_clk_sel_s), .DMONITOROUT (), .TX8B10BEN (1'd1), .LOOPBACK (3'd0), .PHYSTATUS (), - .RXRATE (rx_rate), + .RXRATE (up_rx_rate), .RXVALID (), .RXPD (2'b00), .TXPD (2'b00), .SETERRSTATUS (1'd0), .EYESCANRESET (1'd0), - .RXUSERRDY (rx_user_ready), + .RXUSERRDY (up_rx_user_ready), .EYESCANDATAERROR (), .EYESCANMODE (1'd0), .EYESCANTRIGGER (1'd0), @@ -444,15 +528,15 @@ module util_adxcvr_xch ( .RX8B10BEN (1'd1), .RXUSRCLK (rx_clk), .RXUSRCLK2 (rx_clk), - .RXDATA ({rx_data_open_s, rx_gt_data}), + .RXDATA ({rx_data_open_s, rx_data}), .RXPRBSERR (), .RXPRBSSEL (3'd0), .RXPRBSCNTRESET (1'd0), .RXDFEXYDEN (1'd0), .RXDFEXYDHOLD (1'd0), .RXDFEXYDOVRDEN (1'd0), - .RXDISPERR ({rx_disperr_open_s, rx_gt_disperr}), - .RXNOTINTABLE ({rx_notintable_open_s, rx_gt_notintable}), + .RXDISPERR ({rx_disperr_open_s, rx_disperr}), + .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}), .GTXRXP (rx_p), .GTXRXN (rx_n), .RXBUFRESET (1'd0), @@ -476,8 +560,8 @@ module util_adxcvr_xch ( .RXBYTEREALIGN (), .RXCOMMADET (), .RXCOMMADETEN (1'd1), - .RXMCOMMAALIGNEN (rx_gt_calign), - .RXPCOMMAALIGNEN (rx_gt_calign), + .RXMCOMMAALIGNEN (rx_calign), + .RXPCOMMAALIGNEN (rx_calign), .RXCHANBONDSEQ (), .RXCHBONDEN (1'd0), .RXCHBONDLEVEL (3'd0), @@ -517,17 +601,17 @@ module util_adxcvr_xch ( .RXOUTCLK (rx_out_clk), .RXOUTCLKFABRIC (), .RXOUTCLKPCS (), - .RXOUTCLKSEL (rx_out_clk_sel), + .RXOUTCLKSEL (up_rx_out_clk_sel), .RXDATAVALID (), .RXHEADER (), .RXHEADERVALID (), .RXSTARTOFSEQ (), .RXGEARBOXSLIP (1'd0), - .GTRXRESET (rx_rst), + .GTRXRESET (up_rx_rst), .RXOOBRESET (1'd0), .RXPCSRESET (1'd0), .RXPMARESET (1'd0), - .RXLPMEN (rx_lpm_dfe_n), + .RXLPMEN (up_rx_lpm_dfe_n), .RXCOMSASDET (), .RXCOMWAKEDET (), .RXCOMINITDET (), @@ -536,9 +620,9 @@ module util_adxcvr_xch ( .RXPOLARITY (1'd0), .RXSLIDE (1'd0), .RXCHARISCOMMA (), - .RXCHARISK ({rx_charisk_open_s, rx_gt_charisk}), + .RXCHARISK ({rx_charisk_open_s, rx_charisk}), .RXCHBONDI (5'd0), - .RXRESETDONE (rx_rst_done), + .RXRESETDONE (up_rx_rst_done), .RXQPIEN (1'd0), .RXQPISENN (), .RXQPISENP (), @@ -551,9 +635,9 @@ module util_adxcvr_xch ( .TXQPISTRONGPDOWN (1'd0), .TXQPIWEAKPUP (1'd0), .CFGRESET (1'd0), - .GTTXRESET (tx_rst), + .GTTXRESET (up_tx_rst), .PCSRSVDOUT (), - .TXUSERRDY (tx_user_ready), + .TXUSERRDY (up_tx_user_ready), .GTRESETSEL (1'd0), .RESETOVRD (1'd0), .TXCHARDISPMODE (8'd0), @@ -562,7 +646,7 @@ module util_adxcvr_xch ( .TXUSRCLK2 (tx_clk), .TXELECIDLE (1'd0), .TXMARGIN (3'd0), - .TXRATE (tx_rate), + .TXRATE (up_tx_rate), .TXSWING (1'd0), .TXPRBSFORCEERR (1'd0), .TXDLYBYPASS (1'd1), @@ -588,22 +672,22 @@ module util_adxcvr_xch ( .TXINHIBIT (1'd0), .TXMAINCURSOR (7'b0000000), .TXPISOPD (1'd0), - .TXDATA ({32'd0, tx_gt_data}), + .TXDATA ({32'd0, tx_data}), .GTXTXP (tx_p), .GTXTXN (tx_n), .TXOUTCLK (tx_out_clk), .TXOUTCLKFABRIC (), .TXOUTCLKPCS (), - .TXOUTCLKSEL (tx_out_clk_sel), + .TXOUTCLKSEL (up_tx_out_clk_sel), .TXRATEDONE (), - .TXCHARISK ({4'd0, tx_gt_charisk}), + .TXCHARISK ({4'd0, tx_charisk}), .TXGEARBOXREADY (), .TXHEADER (3'd0), .TXSEQUENCE (7'd0), .TXSTARTSEQ (1'd0), .TXPCSRESET (1'd0), .TXPMARESET (1'd0), - .TXRESETDONE (tx_rst_done), + .TXRESETDONE (up_tx_rst_done), .TXCOMFINISH (), .TXCOMINIT (1'd0), .TXCOMSAS (1'd0), @@ -620,10 +704,10 @@ module util_adxcvr_xch ( generate if (GTH_OR_GTX_N == 1) begin - assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; - assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; - assign rx_pll_clk_sel_s = rx_sys_clk_sel; - assign tx_pll_clk_sel_s = tx_sys_clk_sel; + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; end endgenerate @@ -1025,14 +1109,14 @@ module util_adxcvr_xch ( .CPLLLOCKEN (1'd1), .CPLLPD (1'b0), .CPLLREFCLKSEL (3'b001), - .CPLLRESET (pll_rst), + .CPLLRESET (up_cpll_rst), .DMONFIFORESET (1'd0), .DMONITORCLK (1'd0), - .DRPADDR (up_drp_addr_int[8:0]), + .DRPADDR (up_addr_int[8:0]), .DRPCLK (up_clk), - .DRPDI (up_drp_wdata_int), - .DRPEN (up_drp_enb_int), - .DRPWE (up_drp_wr_int), + .DRPDI (up_wdata_int), + .DRPEN (up_enb_int), + .DRPWE (up_wr_int), .EVODDPHICALDONE (1'd0), .EVODDPHICALSTART (1'd0), .EVODDPHIDRDEN (1'd0), @@ -1047,14 +1131,14 @@ module util_adxcvr_xch ( .GTHRXP (rx_p), .GTNORTHREFCLK0 (1'd0), .GTNORTHREFCLK1 (1'd0), - .GTREFCLK0 (ref_clk), + .GTREFCLK0 (cpll_ref_clk), .GTREFCLK1 (1'd0), .GTRESETSEL (1'd0), .GTRSVD (15'd0), - .GTRXRESET (rx_rst), + .GTRXRESET (up_rx_rst), .GTSOUTHREFCLK0 (1'd0), .GTSOUTHREFCLK1 (1'd0), - .GTTXRESET (tx_rst), + .GTTXRESET (up_tx_rst), .LOOPBACK (3'd0), .LPBKRXTXSEREN (1'd0), .LPBKTXRXSEREN (1'd0), @@ -1065,8 +1149,8 @@ module util_adxcvr_xch ( .PCSRSVDIN (16'd0), .PCSRSVDIN2 (5'd0), .PMARSVDIN (5'd0), - .QPLL0CLK (qpll_clk), - .QPLL0REFCLK (qpll_ref_clk), + .QPLL0CLK (qpll2ch_clk), + .QPLL0REFCLK (qpll2ch_ref_clk), .QPLL1CLK (1'd0), .QPLL1REFCLK (1'd0), .RESETOVRD (1'd0), @@ -1130,7 +1214,7 @@ module util_adxcvr_xch ( .RXELECIDLEMODE (2'b11), .RXGEARBOXSLIP (1'd0), .RXLATCLK (1'd0), - .RXLPMEN (rx_lpm_dfe_n), + .RXLPMEN (up_rx_lpm_dfe_n), .RXLPMGCHOLD (1'd0), .RXLPMGCOVRDEN (1'd0), .RXLPMHFHOLD (1'd0), @@ -1139,7 +1223,7 @@ module util_adxcvr_xch ( .RXLPMLFKLOVRDEN (1'd0), .RXLPMOSHOLD (1'd0), .RXLPMOSOVRDEN (1'd0), - .RXMCOMMAALIGNEN (rx_gt_calign), + .RXMCOMMAALIGNEN (rx_calign), .RXMONITORSEL (2'd0), .RXOOBRESET (1'd0), .RXOSCALRESET (1'd0), @@ -1151,8 +1235,8 @@ module util_adxcvr_xch ( .RXOSINTSTROBE (1'd0), .RXOSINTTESTOVRDEN (1'd0), .RXOSOVRDEN (1'd0), - .RXOUTCLKSEL (rx_out_clk_sel), - .RXPCOMMAALIGNEN (rx_gt_calign), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), .RXPCSRESET (1'd0), .RXPD (2'd0), .RXPHALIGN (1'd0), @@ -1167,7 +1251,7 @@ module util_adxcvr_xch ( .RXPRBSSEL (4'd0), .RXPROGDIVRESET (1'd0), .RXQPIEN (1'd0), - .RXRATE (rx_rate), + .RXRATE (up_rx_rate), .RXRATEMODE (1'd0), .RXSLIDE (1'd0), .RXSLIPOUTCLK (1'd0), @@ -1176,7 +1260,7 @@ module util_adxcvr_xch ( .RXSYNCIN (1'd0), .RXSYNCMODE (1'd0), .RXSYSCLKSEL (rx_sys_clk_sel_s), - .RXUSERRDY (rx_user_ready), + .RXUSERRDY (up_rx_user_ready), .RXUSRCLK (rx_clk), .RXUSRCLK2 (rx_clk), .RX8B10BEN (1'd1), @@ -1188,8 +1272,8 @@ module util_adxcvr_xch ( .TXCOMWAKE (1'd0), .TXCTRL0 (16'd0), .TXCTRL1 (16'd0), - .TXCTRL2 ({4'd0, tx_gt_charisk}), - .TXDATA ({32'd0, tx_gt_data}), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA ({32'd0, tx_data}), .TXDATAEXTENDRSVD (8'd0), .TXDEEMPH (1'd0), .TXDETECTRX (1'd0), @@ -1207,7 +1291,7 @@ module util_adxcvr_xch ( .TXLATCLK (1'd0), .TXMAINCURSOR (7'b1000000), .TXMARGIN (3'd0), - .TXOUTCLKSEL (tx_out_clk_sel), + .TXOUTCLKSEL (up_tx_out_clk_sel), .TXPCSRESET (1'd0), .TXPD (2'd0), .TXPDELECIDLEMODE (1'd0), @@ -1233,11 +1317,11 @@ module util_adxcvr_xch ( .TXPRBSSEL (4'd0), .TXPRECURSOR (5'd0), .TXPRECURSORINV (1'd0), - .TXPROGDIVRESET (tx_rst), + .TXPROGDIVRESET (up_tx_rst), .TXQPIBIASEN (1'd0), .TXQPISTRONGPDOWN (1'd0), .TXQPIWEAKPUP (1'd0), - .TXRATE (tx_rate), + .TXRATE (up_tx_rate), .TXRATEMODE (1'd0), .TXSEQUENCE (7'd0), .TXSWING (1'd0), @@ -1245,7 +1329,7 @@ module util_adxcvr_xch ( .TXSYNCIN (1'd0), .TXSYNCMODE (1'd0), .TXSYSCLKSEL (tx_sys_clk_sel_s), - .TXUSERRDY (tx_user_ready), + .TXUSERRDY (up_tx_user_ready), .TXUSRCLK (tx_clk), .TXUSRCLK2 (tx_clk), .TX8B10BBYPASS (8'd0), @@ -1259,8 +1343,8 @@ module util_adxcvr_xch ( .CPLLLOCK (cpll_locked_s), .CPLLREFCLKLOST (), .DMONITOROUT (), - .DRPDO (up_drp_rdata_s), - .DRPRDY (up_drp_ready_s), + .DRPDO (up_rdata_s), + .DRPRDY (up_ready_s), .EYESCANDATAERROR (), .GTHTXN (tx_n), .GTHTXP (tx_p), @@ -1292,11 +1376,11 @@ module util_adxcvr_xch ( .RXCOMMADET (), .RXCOMSASDET (), .RXCOMWAKEDET (), - .RXCTRL0 ({rx_charisk_open_s, rx_gt_charisk}), - .RXCTRL1 ({rx_disperr_open_s, rx_gt_disperr}), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), .RXCTRL2 (), - .RXCTRL3 ({rx_notintable_open_s, rx_gt_notintable}), - .RXDATA ({rx_data_open_s, rx_gt_data}), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA ({rx_data_open_s, rx_data}), .RXDATAEXTENDRSVD (), .RXDATAVALID (), .RXDLYSRESETDONE (), @@ -1321,7 +1405,7 @@ module util_adxcvr_xch ( .RXQPISENP (), .RXRATEDONE (), .RXRECCLKOUT (), - .RXRESETDONE (rx_rst_done), + .RXRESETDONE (up_rx_rst_done), .RXSLIDERDY (), .RXSLIPDONE (), .RXSLIPOUTCLKRDY (), @@ -1344,7 +1428,7 @@ module util_adxcvr_xch ( .TXQPISENN (), .TXQPISENP (), .TXRATEDONE (), - .TXRESETDONE (tx_rst_done), + .TXRESETDONE (up_tx_rst_done), .TXSYNCDONE (), .TXSYNCOUT ()); end diff --git a/library/util_adxcvr/util_adxcvr_xcm.v b/library/util_adxcvr/util_adxcvr_xcm.v index 6ec6b35df..ba3c88785 100644 --- a/library/util_adxcvr/util_adxcvr_xcm.v +++ b/library/util_adxcvr/util_adxcvr_xcm.v @@ -41,45 +41,83 @@ module util_adxcvr_xcm ( // reset and clocks - input ref_clk, - input pll_rst, - output qpll_clk, - output qpll_ref_clk, - output qpll_locked, - + input qpll_ref_clk, + output qpll2ch_clk, + output qpll2ch_ref_clk, + output qpll2ch_locked, + // drp interface + input up_rstn, input up_clk, - input up_drp_sel, - input [11:0] up_drp_addr, - input up_drp_wr, - input [15:0] up_drp_wdata, - output [15:0] up_drp_rdata, - output up_drp_ready); + input up_qpll_rst, + input [ 7:0] up_cm_sel, + input up_cm_enb, + input [11:0] up_cm_addr, + input up_cm_wr, + input [15:0] up_cm_wdata, + output [15:0] up_cm_rdata, + output up_cm_ready); // parameters + parameter integer XCVR_ID = 0; parameter integer GTH_OR_GTX_N = 0; - parameter integer QPLL_ENABLE = 1; parameter integer QPLL_REFCLK_DIV = 2; parameter integer QPLL_FBDIV_RATIO = 1; parameter [26:0] QPLL_CFG = 27'h06801C1; parameter [ 9:0] QPLL_FBDIV = 10'b0000110000; + // internal registers + + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; + reg [15:0] up_rdata_int = 'd0; + reg up_ready_int = 'd0; + + // internal signals + + wire [15:0] up_rdata_s; + wire up_ready_s; + + // drp access + + assign up_cm_rdata = up_rdata_int; + assign up_cm_ready = up_ready_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + up_rdata_int <= 16'd0; + up_ready_int <= 1'd0; + end else begin + if ((up_cm_sel == XCVR_ID) || (up_cm_sel == 8'hff)) begin + up_enb_int <= up_cm_enb; + up_addr_int <= up_cm_addr; + up_wr_int <= up_cm_wr; + up_wdata_int <= up_cm_wdata; + up_rdata_int <= up_rdata_s; + up_ready_int <= up_ready_s; + end else begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + up_rdata_int <= 16'd0; + up_ready_int <= 1'd0; + end + end + end + // instantiations generate - if (QPLL_ENABLE == 0) begin - assign qpll_clk = 1'd0; - assign qpll_ref_clk = 1'd0; - assign qpll_locked = 1'd0; - assign up_drp_rdata = 16'd0; - assign up_drp_ready = 1'd0; - end - endgenerate - - generate - if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin + if (GTH_OR_GTX_N == 0) begin GTXE2_COMMON #( .SIM_RESET_SPEEDUP ("TRUE"), .SIM_QPLLREFCLK_SEL (3'b001), @@ -102,32 +140,32 @@ module util_adxcvr_xcm ( .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV)) i_gtxe2_common ( .DRPCLK (up_clk), - .DRPEN (up_drp_sel), - .DRPADDR (up_drp_addr[7:0]), - .DRPWE (up_drp_wr), - .DRPDI (up_drp_wdata), - .DRPDO (up_drp_rdata), - .DRPRDY (up_drp_ready), + .DRPEN (up_enb_int), + .DRPADDR (up_addr_int[7:0]), + .DRPWE (up_wr_int), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPRDY (up_ready_s), .GTGREFCLK (1'd0), .GTNORTHREFCLK0 (1'd0), .GTNORTHREFCLK1 (1'd0), - .GTREFCLK0 (ref_clk), + .GTREFCLK0 (qpll_ref_clk), .GTREFCLK1 (1'd0), .GTSOUTHREFCLK0 (1'd0), .GTSOUTHREFCLK1 (1'd0), .QPLLDMONITOR (), - .QPLLOUTCLK (qpll_clk), - .QPLLOUTREFCLK (qpll_ref_clk), + .QPLLOUTCLK (qpll2ch_clk), + .QPLLOUTREFCLK (qpll2ch_ref_clk), .REFCLKOUTMONITOR (), .QPLLFBCLKLOST (), - .QPLLLOCK (qpll_locked), + .QPLLLOCK (qpll2ch_locked), .QPLLLOCKDETCLK (up_clk), .QPLLLOCKEN (1'd1), .QPLLOUTRESET (1'd0), .QPLLPD (1'd0), .QPLLREFCLKLOST (), .QPLLREFCLKSEL (3'b001), - .QPLLRESET (pll_rst), + .QPLLRESET (up_qpll_rst), .QPLLRSVD1 (16'b0000000000000000), .QPLLRSVD2 (5'b11111), .BGBYPASSB (1'd1), @@ -140,7 +178,7 @@ module util_adxcvr_xcm ( endgenerate generate - if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin + if (GTH_OR_GTX_N == 1) begin GTHE3_COMMON #( .SIM_RESET_SPEEDUP ("TRUE"), .SIM_VERSION (2), @@ -221,18 +259,18 @@ module util_adxcvr_xcm ( .BGPDB (1'd1), .BGRCALOVRD (5'b11111), .BGRCALOVRDENB (1'd1), - .DRPADDR (up_drp_addr[8:0]), + .DRPADDR (up_addr_int[8:0]), .DRPCLK (up_clk), - .DRPDI (up_drp_wdata), - .DRPEN (up_drp_sel), - .DRPWE (up_drp_wr), + .DRPDI (up_wdata_int), + .DRPEN (up_enb_int), + .DRPWE (up_wr_int), .GTGREFCLK0 (1'd0), .GTGREFCLK1 (1'd0), .GTNORTHREFCLK00 (1'd0), .GTNORTHREFCLK01 (1'd0), .GTNORTHREFCLK10 (1'd0), .GTNORTHREFCLK11 (1'd0), - .GTREFCLK00 (ref_clk), + .GTREFCLK00 (qpll_ref_clk), .GTREFCLK01 (1'd0), .GTREFCLK10 (1'd0), .GTREFCLK11 (1'd0), @@ -252,7 +290,7 @@ module util_adxcvr_xcm ( .QPLL0LOCKEN (1'd1), .QPLL0PD (1'd0), .QPLL0REFCLKSEL (3'b001), - .QPLL0RESET (pll_rst), + .QPLL0RESET (up_qpll_rst), .QPLL1CLKRSVD0 (1'd0), .QPLL1CLKRSVD1 (1'd0), .QPLL1LOCKDETCLK (1'd0), @@ -261,16 +299,16 @@ module util_adxcvr_xcm ( .QPLL1REFCLKSEL (3'b001), .QPLL1RESET (1'd1), .RCALENB (1'd1), - .DRPDO (up_drp_rdata), - .DRPRDY (up_drp_ready), + .DRPDO (up_rdata_s), + .DRPRDY (up_ready_s), .PMARSVDOUT0 (), .PMARSVDOUT1 (), .QPLLDMONITOR0 (), .QPLLDMONITOR1 (), .QPLL0FBCLKLOST (), - .QPLL0LOCK (qpll_locked), - .QPLL0OUTCLK (qpll_clk), - .QPLL0OUTREFCLK (qpll_ref_clk), + .QPLL0LOCK (qpll2ch_locked), + .QPLL0OUTCLK (qpll2ch_clk), + .QPLL0OUTREFCLK (qpll2ch_ref_clk), .QPLL0REFCLKLOST (), .QPLL1FBCLKLOST (), .QPLL1LOCK (),