diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
index 2efc1bb8c..d6a6668d0 100644
--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@@ -103,46 +103,6 @@ foreach p $dummy_axi_ports {
 	adi_set_ports_dependency $p "0"
 }
 
-# These are in the design to keep the Altera tools happy which can't handle
-# uni-directional AXI interfaces. The Xilinx tools can and do a better job when
-# they know that the interface is uni-directional, so disable the ports.
-set dummy_axi_ports [list \
-	"m_dest_axi_arvalid" \
-	"m_dest_axi_arready" \
-	"m_dest_axi_araddr" \
-	"m_dest_axi_arlen" \
-	"m_dest_axi_arsize" \
-	"m_dest_axi_arburst" \
-	"m_dest_axi_arcache" \
-	"m_dest_axi_arprot" \
-	"m_dest_axi_rready" \
-	"m_dest_axi_rvalid" \
-	"m_dest_axi_rresp" \
-	"m_dest_axi_rdata" \
-	"m_src_axi_awvalid" \
-	"m_src_axi_awready" \
-	"m_src_axi_awvalid" \
-	"m_src_axi_awaddr" \
-	"m_src_axi_awlen" \
-	"m_src_axi_awsize" \
-	"m_src_axi_awburst" \
-	"m_src_axi_awcache" \
-	"m_src_axi_awprot" \
-	"m_src_axi_wvalid" \
-	"m_src_axi_wready" \
-	"m_src_axi_wvalid" \
-	"m_src_axi_wdata" \
-	"m_src_axi_wstrb" \
-	"m_src_axi_wlast" \
-	"m_src_axi_bready" \
-	"m_src_axi_bvalid" \
-	"m_src_axi_bresp" \
-]
-
-foreach p $dummy_axi_ports {
-	adi_set_ports_dependency $p "0"
-}
-
 adi_add_bus "fifo_wr" "slave" \
 	"analog.com:interface:fifo_wr_rtl:1.0" \
 	"analog.com:interface:fifo_wr:1.0" \
diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl
index 839c34c3f..d71659a1a 100644
--- a/projects/usdrx1/common/usdrx1_bd.tcl
+++ b/projects/usdrx1/common/usdrx1_bd.tcl
@@ -61,6 +61,8 @@ set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3
 set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd]
 set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
 set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
+set_property -dict [list CONFIG.GT_Line_Rate {3.2}  ] $axi_usdrx1_jesd
+set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ]  $axi_usdrx1_jesd
 
 set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
 set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt