From f5de5ca4871be3dce4797064db0d9d8181432a01 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 19 Aug 2015 10:12:24 +0300 Subject: [PATCH 01/19] usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism --- library/axi_ad9671/axi_ad9671_if.v | 4 ++-- projects/usdrx1/common/usdrx1_bd.tcl | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index dccb5669d..ec99d3e17 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -201,12 +201,12 @@ module axi_ad9671_if ( adc_raddr_out <= 4'h8; adc_sync_status <= 1'b0; end else begin - if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin adc_sync_status <= 1'b0; end else if(adc_sync_s == 1'b1) begin adc_sync_status <= 1'b1; end - if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin adc_waddr <= 4'h0; adc_raddr_out <= 4'h8; end else if (int_valid == 1'b1) begin diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 69c14e2ac..c8a96a2d9 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -66,6 +66,8 @@ set_property -dict [list CONFIG.PCORE_ID {3}] $axi_ad9671_core_3 set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd +set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd +set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ] $axi_usdrx1_jesd set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] [get_bd_cells axi_usdrx1_gt] From 114d48d4e1e56c0eb0b2ba005500bed0ef084eb3 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 18 Aug 2015 14:13:55 +0200 Subject: [PATCH 02/19] axi_dmac: Fix a bug occuring on transfers < one beat Signed-off-by: Paul Cercueil --- library/axi_dmac/address_generator.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index b420fb0e1..9fcce1ba3 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -103,7 +103,7 @@ end always @(posedge clk) begin if (addr_valid == 1'b0) begin if (eot == 1'b1) - length <= req_last_burst_length; + length <= last_burst_len; else length <= MAX_BEATS_PER_BURST - 1; end @@ -130,6 +130,7 @@ always @(posedge clk) begin if (req_valid && enable) begin address <= req_address; req_ready <= 1'b0; + last_burst_len <= req_last_burst_length; end end else begin if (addr_valid && addr_ready) begin From 37c14e782da6147d4cb0ecb7823e99213e711d19 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 20 Aug 2015 18:12:04 +0200 Subject: [PATCH 03/19] axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index cf43b0b2a..2edd47838 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -64,6 +64,46 @@ adi_set_bus_dependency "m_axis" "m_axis" \ adi_set_ports_dependency "fifo_rd" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_DEST')) = 2)" +# These are in the design to keep the Altera tools happy which can't handle +# uni-directional AXI interfaces. The Xilinx tools can and do a better job when +# they know that the interface is uni-directional, so disable the ports. +set dummy_axi_ports [list \ + "m_dest_axi_arvalid" \ + "m_dest_axi_arready" \ + "m_dest_axi_araddr" \ + "m_dest_axi_arlen" \ + "m_dest_axi_arsize" \ + "m_dest_axi_arburst" \ + "m_dest_axi_arcache" \ + "m_dest_axi_arprot" \ + "m_dest_axi_rready" \ + "m_dest_axi_rvalid" \ + "m_dest_axi_rresp" \ + "m_dest_axi_rdata" \ + "m_src_axi_awvalid" \ + "m_src_axi_awready" \ + "m_src_axi_awvalid" \ + "m_src_axi_awaddr" \ + "m_src_axi_awlen" \ + "m_src_axi_awsize" \ + "m_src_axi_awburst" \ + "m_src_axi_awcache" \ + "m_src_axi_awprot" \ + "m_src_axi_wvalid" \ + "m_src_axi_wready" \ + "m_src_axi_wvalid" \ + "m_src_axi_wdata" \ + "m_src_axi_wstrb" \ + "m_src_axi_wlast" \ + "m_src_axi_bready" \ + "m_src_axi_bvalid" \ + "m_src_axi_bresp" \ +] + +foreach p $dummy_axi_ports { + adi_set_ports_dependency $p "0" +} + adi_add_bus "fifo_wr" "slave" \ "analog.com:interface:fifo_wr_rtl:1.0" \ "analog.com:interface:fifo_wr:1.0" \ From b7de542e26e08bfdd83c892b6dd1442795bae779 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 1 Sep 2015 10:35:35 +0200 Subject: [PATCH 04/19] usdrx1: Disable SYNC_TRANSFER_START for the DMA There is no sync signal in this design, so the flag needs to be set to 0. Signed-off-by: Lars-Peter Clausen --- projects/usdrx1/common/usdrx1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index c8a96a2d9..3e19a4f61 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -86,7 +86,7 @@ set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma From b73430d7eea83a8cfd05b7bd72e2719f9bd9e3e7 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 1 Sep 2015 10:38:18 +0200 Subject: [PATCH 05/19] usdrx1: Add overflow flag to ILA It's useful to know if and when a overflow happens. Signed-off-by: Lars-Peter Clausen --- projects/usdrx1/common/usdrx1_bd.tcl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 3e19a4f61..c61ef941f 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -258,7 +258,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE1_WIDTH {8}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_ad9671 @@ -267,6 +267,7 @@ set_property -dict [list CONFIG.C_PROBE4_WIDTH {128}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE5_WIDTH {8}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE6_WIDTH {128}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE7_WIDTH {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE8_WIDTH {1}] $ila_ad9671 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9671 ad_connect axi_ad9671_core_0/adc_clk ila_ad9671/CLK @@ -278,3 +279,4 @@ ad_connect adc_data_2 ila_ad9671/PROBE4 ad_connect adc_valid_2 ila_ad9671/PROBE5 ad_connect adc_data_3 ila_ad9671/PROBE6 ad_connect adc_valid_3 ila_ad9671/PROBE7 +ad_connect adc_dovf_0 ila_ad9671/PROBE8 From c00a6af4db165f032a36553dc6e4535c9816ec79 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 1 Sep 2015 10:42:06 +0200 Subject: [PATCH 06/19] usdrx1: Add DDR FIFO The converters on the usdrx1 generate 2.5GB/s. This more than we can transport over the HP interconnects to the system memory. Add a dedicated DDR FIFO to design which can be used to buffer the data before it is transferred to the main memory. Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA FIFO size from 4 to 8, so we can transfer the captured data faster to the main memory. Signed-off-by: Lars-Peter Clausen --- projects/usdrx1/common/usdrx1_bd.tcl | 30 ++++++++---- projects/usdrx1/zc706/system_bd.tcl | 20 +++++++- projects/usdrx1/zc706/system_project.tcl | 1 + projects/usdrx1/zc706/system_top.v | 58 ++++++++++++++++++++++++ 4 files changed, 99 insertions(+), 10 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index c61ef941f..cf8fb263f 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -80,18 +80,21 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_usdrx1_dma set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_usdrx1_spi] set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi @@ -201,7 +204,7 @@ ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data ad_connect gt_rx_sof_2 axi_ad9671_core_2/rx_sof ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data ad_connect gt_rx_sof_3 axi_ad9671_core_3/rx_sof -ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk +ad_connect axi_ad9671_core_0/adc_clk usdrx1_fifo/adc_clk ad_connect adc_data_0 axi_ad9671_core_0/adc_data ad_connect adc_data_1 axi_ad9671_core_1/adc_data ad_connect adc_data_2 axi_ad9671_core_2/adc_data @@ -218,9 +221,8 @@ ad_connect adc_dovf_0 axi_ad9671_core_0/adc_dovf ad_connect adc_dovf_1 axi_ad9671_core_1/adc_dovf ad_connect adc_dovf_2 axi_ad9671_core_2/adc_dovf ad_connect adc_dovf_3 axi_ad9671_core_3/adc_dovf -ad_connect adc_wr_en axi_usdrx1_dma/fifo_wr_en -ad_connect adc_data axi_usdrx1_dma/fifo_wr_din -ad_connect adc_dovf axi_usdrx1_dma/fifo_wr_overflow +ad_connect adc_wr_en usdrx1_fifo/adc_wr +ad_connect adc_data usdrx1_fifo/adc_wdata ad_connect axi_ad9671_adc_raddr axi_ad9671_core_0/adc_raddr_out ad_connect axi_ad9671_adc_raddr axi_ad9671_core_1/adc_raddr_in ad_connect axi_ad9671_adc_raddr axi_ad9671_core_2/adc_raddr_in @@ -230,6 +232,16 @@ ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in +ad_connect axi_usdrx1_gt/rx_rst usdrx1_fifo/adc_rst +ad_connect adc_dovf usdrx1_fifo/adc_wovf + +ad_connect usdrx1_fifo/dma_wdata axi_usdrx1_dma/s_axis_data +ad_connect usdrx1_fifo/dma_wr axi_usdrx1_dma/s_axis_valid +ad_connect usdrx1_fifo/dma_wready axi_usdrx1_dma/s_axis_ready +ad_connect usdrx1_fifo/dma_xfer_req axi_usdrx1_dma/s_axis_xfer_req +ad_connect sys_200m_clk axi_usdrx1_dma/s_axis_aclk +ad_connect sys_200m_clk usdrx1_fifo/dma_clk + # address map ad_cpu_interconnect 0x44A00000 axi_ad9671_core_0 @@ -242,9 +254,9 @@ ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_cpu_clk axi_usdrx1_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn +ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi +ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi diff --git a/projects/usdrx1/zc706/system_bd.tcl b/projects/usdrx1/zc706/system_bd.tcl index 18ec3434c..0657c681c 100644 --- a/projects/usdrx1/zc706/system_bd.tcl +++ b/projects/usdrx1/zc706/system_bd.tcl @@ -1,4 +1,22 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source ../common/usdrx1_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512 + +create_bd_port -dir I -type rst sys_rst +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + +ad_connect sys_rst usdrx1_fifo/sys_rst +ad_connect sys_clk usdrx1_fifo/sys_clk +ad_connect ddr3 usdrx1_fifo/ddr3 + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ + [get_bd_addr_spaces usdrx1_fifo/axi_adcfifo/axi] \ + [get_bd_addr_segs usdrx1_fifo/axi_ddr_cntrl/memmap/memaddr] \ + SEG_axi_ddr_cntrl_memaddr + +source ../common/usdrx1_bd.tcl diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl index 629ece234..e022ae874 100644 --- a/projects/usdrx1/zc706/system_project.tcl +++ b/projects/usdrx1/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files usdrx1_zc706 [list \ "system_top.v" \ "system_constr.xdc" \ "../common/usdrx1_spi.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] adi_project_run usdrx1_zc706 diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index ca07ae87e..c73b1a051 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -74,6 +74,26 @@ module system_top ( spdif, + sys_rst, + sys_clk_p, + sys_clk_n, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n, + iic_scl, iic_sda, @@ -152,6 +172,26 @@ module system_top ( output spdif; + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; + inout iic_scl; inout iic_sda; @@ -360,6 +400,24 @@ module system_top ( endgenerate system_wrapper i_system_wrapper ( + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), From 7c896ba5f8ee2999cdbbd6e05d925d6abdfdbf7d Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 14 Sep 2015 18:20:30 +0300 Subject: [PATCH 07/19] axi_ad9361: Fixed constraints definition --- library/axi_ad9361/axi_ad9361_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 114786bd3..e915e02f5 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -41,7 +41,7 @@ adi_ip_files axi_ad9361 [list \ "axi_ad9361.v" ] adi_ip_properties axi_ad9361 -adi_ip_constraints axi_dmac "axi_ad9361_constr.xdc" "late" +adi_ip_constraints axi_ad9361 "axi_ad9361_constr.xdc" "late" set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] From 522f30ce213fe64a88bfb47f50fe26300e85d55e Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 15 Sep 2015 18:59:35 +0200 Subject: [PATCH 08/19] adi_ip.tcl: Add helper function to add TTCL files to a core Add a helper function which allows to add TTCL templates files to a core. Signed-off-by: Lars-Peter Clausen --- library/scripts/adi_ip.tcl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index b13f4efa6..572c407aa 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -56,6 +56,15 @@ proc adi_ip_constraints {ip_name ip_constr_files {processing_order late}} { ] $f } +proc adi_ip_ttcl {ip_name ip_constr_files} { + + set proj_filegroup [ipx::get_file_groups xilinx_v*synthesis -of_objects [ipx::current_core]] + set f [ipx::add_file $ip_constr_files $proj_filegroup] + set_property -dict [list \ + type ttcl \ + ] $f +} + proc adi_ip_properties {ip_name} { ipx::package_project -root_dir . From 5af371db6be3d7a8801eee7f57d765bf1fabe72a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 15 Sep 2015 18:58:40 +0200 Subject: [PATCH 09/19] axi_dmac: Generate per core instance constraint file When having multiple DMA cores sharing the same constraint file Vivado seems to apply the constraints from the first core to all the other cores when re-running synthesis and implementation from within the Vivado GUI. This causes wrong timing constraints if the DMA cores have different configurations. To avoid this issue use a TTCL template that generates a custom constraint file for each DMA core instance. This also allows us to drop the asynchronous clock detection hack from the constraint file and move it to the template and only generate the CDC constraints if the clock domains are asynchronous. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/Makefile | 2 +- library/axi_dmac/axi_dmac_constr.ttcl | 164 +++++++++++++++++++++ library/axi_dmac/axi_dmac_constr.xdc | 197 -------------------------- library/axi_dmac/axi_dmac_ip.tcl | 4 +- 4 files changed, 167 insertions(+), 200 deletions(-) create mode 100644 library/axi_dmac/axi_dmac_constr.ttcl delete mode 100644 library/axi_dmac/axi_dmac_constr.xdc diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile index 211223fdb..a8eb95a83 100644 --- a/library/axi_dmac/Makefile +++ b/library/axi_dmac/Makefile @@ -26,7 +26,7 @@ M_DEPS += src_fifo_inf.v M_DEPS += splitter.v M_DEPS += response_generator.v M_DEPS += axi_dmac.v -M_DEPS += axi_dmac_constr.xdc +M_DEPS += axi_dmac_constr.ttcl M_DEPS += ../util_axis_resize/util_axis_resize.xpr M_DEPS += ../util_axis_fifo/util_axis_fifo.xpr diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl new file mode 100644 index 000000000..796d513cd --- /dev/null +++ b/library/axi_dmac/axi_dmac_constr.ttcl @@ -0,0 +1,164 @@ +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_dest_req [getBooleanValue "C_CLKS_ASYNC_DEST_REQ"] :> +<: set async_req_src [getBooleanValue "C_CLKS_ASYNC_REQ_SRC"] :> +<: set async_src_dest [getBooleanValue "C_CLKS_ASYNC_SRC_DEST"] :> + +set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]] +set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hier *cdc_sync_stage2_reg*] + +<: if {$async_req_src} { :> +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *eot_mem_reg* \ + -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +<: } :> +<: if {$async_dest_req} { :> +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $dest_clk] + +set_false_path -quiet \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $req_clk] +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *eot_mem_reg* \ + -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +<: } :> +<: if {$async_src_dest} { :> +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + [get_property -min PERIOD $dest_clk] + +# Not sure why, but it seems the built-in constraints for the RAM36B are wrong +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \ + [get_property -min PERIOD $dest_clk] + +<: } :> +# Reset signals +set_false_path -quiet \ + -from $req_clk \ + -to [get_pins -quiet -hier *reset_shift_reg*/PRE] + +# Ignore timing for debug signals to register map +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] diff --git a/library/axi_dmac/axi_dmac_constr.xdc b/library/axi_dmac/axi_dmac_constr.xdc deleted file mode 100644 index e3e8e0ac1..000000000 --- a/library/axi_dmac/axi_dmac_constr.xdc +++ /dev/null @@ -1,197 +0,0 @@ - -set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]] -set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]] -set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]] - -# if ... else does not work in xdc files, but expr, well ok... -set async_src_to_req_clk [expr {$req_clk != $src_clk ? $src_clk : {}}] -set async_req_to_src_clk [expr {$req_clk != $src_clk ? $req_clk : {}}] -set async_dest_to_req_clk [expr {$req_clk != $dest_clk ? $dest_clk : {}}] -set async_req_to_dest_clk [expr {$req_clk != $dest_clk ? $req_clk : {}}] -set async_dest_to_src_clk [expr {$src_clk != $dest_clk ? $dest_clk : {}}] -set async_src_to_dest_clk [expr {$src_clk != $dest_clk ? $src_clk : {}}] - -set_property ASYNC_REG TRUE \ - [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ - [get_cells -quiet -hier *cdc_sync_stage2_reg*] - -#proc get_flops {name inst} { -# return [get_cells -hier $name \ -# -filter [format {NAME =~ *%s* && PRIMITIVE_SUBGROUP == flop} $name]] -#} -# -#proc set_single_bit_cdc_constraints {name clk} { -# set_false_path -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}] -#} -# -#proc set_multi_bit_cdc_constraints {name clk} { -# set_max_delay -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}] \ -# [get_property PERIOD $clk] -datapath_only -#} -# -#proc set_fifo_cdc_constraints {name clk_a clk_b} { -# set_multi_bit_cdc_constraints ${name}/i_waddr_sync $clk_a -# set_multi_bit_cdc_constraints ${name}/i_raddr_sync $clk_b -# set_max_delay -from [get_flops *cdc_sync_fifo_ram_reg* ${name}] -to $clk_b [get_property PERIOD $clk_b] -datapath_only -#} - -#set_multi_bit_constraints i_sync_src_request_id $req_clk -#set_multi_bit_constraints i_sync_dest_request_id $src_clk -#set_multi_bit_constraints i_sync_req_response_id $dest_clk - -set_max_delay -quiet \ - -from $async_req_to_src_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $req_clk] -datapath_only -set_max_delay -quiet \ - -from $async_src_to_dest_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $src_clk] -datapath_only -set_max_delay -quiet \ - -from $async_dest_to_req_clk \ - -to [get_cells -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $dest_clk] -datapath_only - -#set_single_bit_cdc_constraints i_sync_status_src $src_clk -#set_single_bit_cdc_constraints i_sync_control_src $req_clk -#set_single_bit_cdc_constraints i_sync_status_dest $dest_clk -#set_single_bit_cdc_constraints i_sync_control_dest $req_clk - -set_false_path -quiet \ - -from $async_src_to_req_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}] -set_false_path -quiet \ - -from $async_req_to_src_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}] -set_false_path -quiet \ - -from $async_dest_to_req_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}] -set_false_path -quiet \ - -from $async_req_to_dest_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}] - -#set_fifo_cdc_constraints i_dest_req_fifo $req_clk $dest_clk -#set_fifo_cdc_constraints i_dest_response_fifo $dest_clk $req_clk -#set_fifo_cdc_constraints i_src_req_fifo $req_clk $src_clk -#set_fifo_cdc_constraints i_src_response_fifo $src_clk $req_clk - -set_max_delay -quiet \ - -from $async_req_to_dest_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $req_clk] -datapath_only -set_max_delay -quiet \ - -from $async_dest_to_req_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $dest_clk] -datapath_only -set_max_delay -quiet \ - -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ - -to $async_dest_to_req_clk \ - [get_property PERIOD $dest_clk] -datapath_only - -set_max_delay -quiet \ - -from $async_dest_to_req_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $dest_clk] -datapath_only -set_max_delay -quiet \ - -from $async_req_to_dest_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $req_clk] -datapath_only -set_max_delay -quiet \ - -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \ - -to $async_req_to_dest_clk \ - [get_property PERIOD $req_clk] -datapath_only - -set_max_delay -quiet \ - -from $async_req_to_src_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $req_clk] -datapath_only -set_max_delay -quiet \ - -from $async_src_to_req_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $src_clk] -datapath_only -set_max_delay -quiet \ - -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ - -to $async_src_to_req_clk \ - [get_property PERIOD $src_clk] -datapath_only - -#set_max_delay \ -# -from $src_clk \ -# -to [get_cells -hier *cdc_sync_stage1_reg* \ -# -filter {NAME =~ *i_src_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ -# [get_property PERIOD $src_clk] -datapath_only -#set_max_delay \ -# -from $req_clk \ -# -to [get_cells -hier *cdc_sync_stage1_reg* \ -# -filter {NAME =~ *i_src_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ -# [get_property PERIOD $req_clk] -datapath_only -#set_max_delay \ -# -from [get_cells -hier *cdc_sync_fifo_ram_reg* \ -# -filter {NAME =~ *i_src_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \ -# -to $req_clk \ -# [get_property PERIOD $req_clk] -datapath_only - -#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only -#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only -set_max_delay -quiet \ - -from [get_cells -quiet -hier *eot_mem_reg* \ - -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ - -to $async_src_to_req_clk [get_property PERIOD $src_clk] -datapath_only -set_max_delay -quiet \ - -from [get_cells -quiet -hier *eot_mem_reg* \ - -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ - -to $async_dest_to_req_clk [get_property PERIOD $dest_clk] -datapath_only - -#set_fifo_cdc_constraints i_fifo $src_clk $dest_clk -set_max_delay -quiet \ - -from $async_src_to_dest_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $src_clk] -datapath_only -set_max_delay -quiet \ - -from $async_dest_to_src_clk \ - -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ - [get_property PERIOD $dest_clk] -datapath_only - -# Reset signals -set_false_path -quiet \ - -from $req_clk \ - -to [get_pins -quiet -hier *reset_shift_reg*/PRE] - -# Not sure why, but it seems the built-in constraints for the RAM36B are wrong -set_max_delay -quiet \ - -from $async_dest_to_src_clk \ - -to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \ - [get_property PERIOD $dest_clk] -datapath_only - -# Ignore timing for debug signals to register map -set_false_path -quiet \ - -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ - -filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] -set_false_path -quiet \ - -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ - -filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] -set_false_path -quiet \ - -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] -set_false_path -quiet \ - -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 2edd47838..3080d92bb 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -23,10 +23,10 @@ adi_ip_files axi_dmac [list \ "splitter.v" \ "response_generator.v" \ "axi_dmac.v" \ - "axi_dmac_constr.xdc" ] + "axi_dmac_constr.ttcl" ] adi_ip_properties axi_dmac -adi_ip_constraints axi_dmac "axi_dmac_constr.xdc" "late" +adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl" adi_ip_add_core_dependencies { \ analog.com:user:util_axis_resize:1.0 \ From 052860cbc35c49ec8a46ad0a09287948bdc3d08f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Sep 2015 17:32:24 +0200 Subject: [PATCH 10/19] axi_dmac: Fix source pause signal For the source controller use the pause signal that has been properly transferred to the source clock domain rather than the pause signal from the request clock domain. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 4a2b68874..84d2e3e6f 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -618,7 +618,7 @@ dmac_src_mm_axi #( .m_axi_aclk(m_src_axi_aclk), .m_axi_aresetn(src_resetn), - .pause(pause), + .pause(src_pause), .enable(src_enable), .enabled(src_enabled), .sync_id(src_sync_id), From ab8256cf924bf1d6daa7b4f9807db22682a4b161 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 22 Sep 2015 10:33:50 +0300 Subject: [PATCH 11/19] ad_tdd_control: Redesign the state machine to prevent timing failure. --- library/common/ad_tdd_control.v | 120 ++++++++++++++++++-------------- 1 file changed, 67 insertions(+), 53 deletions(-) diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index d36ad06f1..199997cc3 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -145,7 +145,8 @@ module ad_tdd_control( reg [23:0] tdd_counter = 24'h0; reg [ 5:0] tdd_burst_counter = 6'h0; - reg tdd_counter_state = OFF; + reg tdd_cstate = OFF; + reg tdd_cstate_next = OFF; reg counter_at_tdd_vco_rx_on_1 = 1'b0; reg counter_at_tdd_vco_rx_off_1 = 1'b0; @@ -169,6 +170,7 @@ module ad_tdd_control( reg counter_at_tdd_tx_dp_off_2 = 1'b0; reg tdd_enable_d = 1'h0; + reg tdd_last_burst = 1'b0; // internal signals @@ -176,7 +178,8 @@ module ad_tdd_control( wire [23:0] tdd_tx_dp_on_2_s; wire [23:0] tdd_tx_dp_off_1_s; wire [23:0] tdd_tx_dp_off_2_s; - + wire tdd_endof_frame; + wire tdd_endof_burst; wire tdd_txrx_only_en_s; assign tdd_counter_status = tdd_counter; @@ -186,49 +189,60 @@ module ad_tdd_control( // *************************************************************************** always @(posedge clk) begin - - // sync reset if (rst == 1'b1) begin - tdd_counter <= 24'h0; - tdd_counter_state <= OFF; + tdd_cstate <= OFF; + tdd_enable_d <= 0; end else begin - + tdd_cstate <= tdd_cstate_next; tdd_enable_d <= tdd_enable; + end + end - // counter reset - if (tdd_enable == 1'b0) begin - tdd_counter_state <= OFF; - end else + always @* begin + tdd_cstate_next <= tdd_cstate; - // start counter on the positive edge of the tdd_enable - if ((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin - tdd_counter <= tdd_counter_init; - tdd_burst_counter <= tdd_burst_count; - tdd_counter_state <= ON; - end else - - // free running counter - if (tdd_counter_state == ON) begin - if (tdd_counter == tdd_frame_length) begin - tdd_counter <= 22'h0; - if (tdd_burst_counter > 1) begin // inside a burst - tdd_burst_counter <= tdd_burst_counter - 1; - tdd_counter_state <= ON; - end - else - if ( tdd_burst_counter == 1) begin // end of burst - tdd_burst_counter <= 6'h0; - tdd_counter_state <= OFF; - end - else begin // contiuous mode - tdd_burst_counter <= 6'h0; - tdd_counter_state <= ON; - end - end - else begin - tdd_counter <= tdd_counter + 1; + case (tdd_cstate) + ON : begin + if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin + tdd_cstate_next <= OFF; end end + + OFF : begin + if((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin + tdd_cstate_next <= ON; + end + end + endcase + end + + assign tdd_endof_frame = (tdd_counter == tdd_frame_length) ? 1'b1 : 1'b0; + assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_counter == tdd_frame_length)) ? 1'b1 : 1'b0; + + // tdd free running counter + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_counter <= tdd_counter_init; + end else begin + if (tdd_cstate == ON) begin + tdd_counter <= (tdd_counter < tdd_frame_length) ? tdd_counter + 1 : 24'b0; + end else begin + tdd_counter <= tdd_counter_init; + end + end + end + + // tdd burst counter + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_burst_counter <= tdd_burst_count; + end else begin + if (tdd_cstate == ON) begin + tdd_burst_counter <= ((tdd_burst_counter > 0) && (tdd_endof_frame == 1'b1)) ? tdd_burst_counter - 1 : tdd_burst_counter; + end else begin + tdd_burst_counter <= tdd_burst_count; + end + tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0; end end @@ -539,13 +553,13 @@ module ad_tdd_control( if(rst == 1'b1) begin tdd_rx_vco_en <= 1'b0; end - else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin + else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin tdd_rx_vco_en <= 1'b0; end - else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin + else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin tdd_rx_vco_en <= 1'b1; end - else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin tdd_rx_vco_en <= tdd_rx_only; end else begin @@ -557,13 +571,13 @@ module ad_tdd_control( if(rst == 1'b1) begin tdd_tx_vco_en <= 1'b0; end - else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin + else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin tdd_tx_vco_en <= 1'b0; end - else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin + else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin tdd_tx_vco_en <= 1'b1; end - else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin tdd_tx_vco_en <= tdd_tx_only; end else begin @@ -575,13 +589,13 @@ module ad_tdd_control( if(rst == 1'b1) begin tdd_rx_rf_en <= 1'b0; end - else if((tdd_counter_state == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin + else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin tdd_rx_rf_en <= 1'b0; end - else if((tdd_counter_state == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin + else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin tdd_rx_rf_en <= 1'b1; end - else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin tdd_rx_rf_en <= tdd_rx_only; end else begin @@ -593,13 +607,13 @@ module ad_tdd_control( if(rst == 1'b1) begin tdd_tx_rf_en <= 1'b0; end - else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin + else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin tdd_tx_rf_en <= 1'b0; end - else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin + else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin tdd_tx_rf_en <= 1'b1; end - else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin tdd_tx_rf_en <= tdd_tx_only; end else begin @@ -611,13 +625,13 @@ module ad_tdd_control( if(rst == 1'b1) begin tdd_tx_dp_en <= 1'b0; end - else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin + else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin tdd_tx_dp_en <= 1'b0; end - else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin + else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin tdd_tx_dp_en <= 1'b1; end - else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin tdd_tx_dp_en <= tdd_tx_only; end else begin From 0a4f43efea4bc9757a69c8348d9e1a0c734a4659 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Sep 2015 11:11:29 +0300 Subject: [PATCH 12/19] axi_ad9144: Clock ratio is indicating a sampling clock ratio The software can use this data to calculate the effective sampling clock, independent of the interface type. --- library/axi_ad9144/axi_ad9144_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index e662bfe00..871a32970 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -295,7 +295,7 @@ module axi_ad9144_core ( .dac_status (1'b1), .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd40), + .dac_clk_ratio (32'd4), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), From d45f49c0625d009ad7c5a3f28cef72a5a527a0d8 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Sep 2015 11:12:36 +0300 Subject: [PATCH 13/19] axi_ad9152: Clock ratio is indicating a sampling clock ratio The software can use this data to calculate the effective sampling clock, independent of the interface type. --- library/axi_ad9152/axi_ad9152_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v index ae91a3cc1..52334b3a6 100644 --- a/library/axi_ad9152/axi_ad9152_core.v +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -219,7 +219,7 @@ module axi_ad9152_core ( .dac_status (1'b1), .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd40), + .dac_clk_ratio (32'd4), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), From edb94ada8b018ebbbfd21cb8c3189641cbc18835 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Sep 2015 11:13:20 +0300 Subject: [PATCH 14/19] axi_ad9234: Clock ratio is indicating a sampling clock ratio The software can use this data to calculate the effective sampling clock, independent of the interface type. --- library/axi_ad9234/axi_ad9234.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index 1148a07b4..1eb18c72f 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -261,7 +261,7 @@ module axi_ad9234 ( .adc_sync_status (1'd0), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), - .adc_clk_ratio (32'd40), + .adc_clk_ratio (32'd4), .adc_start_code (), .adc_sync (), .up_status_pn_err (up_status_pn_err), From 5e082be9637888fd0c024f4fde16647e97da4627 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 24 Sep 2015 11:14:01 +0300 Subject: [PATCH 15/19] axi_ad9680: Clock ratio is indicating a sampling clock ratio The software can use this data to calculate the effective sampling clock, independent of the interface type. --- library/axi_ad9680/axi_ad9680.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 6abbf52a1..aa60bdcf9 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -263,7 +263,7 @@ module axi_ad9680 ( .adc_sync_status (1'd0), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), - .adc_clk_ratio (32'd40), + .adc_clk_ratio (32'd4), .adc_start_code (), .adc_sync (), .up_status_pn_err (up_status_pn_err), From 1ebd38c514845a59911f00149e5d5c25529b5538 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 8 Oct 2015 16:50:36 +0300 Subject: [PATCH 16/19] util_dacfifo: Update read out method Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address. --- library/util_dacfifo/util_dacfifo.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index ccd2097b1..8a0f0bb9f 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -112,7 +112,7 @@ module util_dacfifo ( always @(posedge dma_clk) begin if(dma_rst == 1'b1) begin dma_waddr <= 'b0; - dma_lastaddr <= {ADDR_WIDTH{1'b1}}; + dma_lastaddr <= 'b0; end else begin if (dma_valid && dma_xfer_req) begin dma_waddr <= dma_waddr + 1; @@ -137,7 +137,11 @@ module util_dacfifo ( // generate dac read address always @(posedge dac_clk) begin if(dac_valid == 1'b1) begin - dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; + if (dma_lastaddr_2d == 'h0) begin + dac_raddr <= dac_raddr + 1; + end else begin + dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; + end end dac_data <= dac_data_s; end From e4517c0d6a24b0f00763166d76f3af822f3a95af Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 8 Oct 2015 16:51:08 +0300 Subject: [PATCH 17/19] daq2/common: Connect reset to dac fifo --- projects/daq2/common/daq2_bd.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index c05e87626..6d744a16b 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -131,6 +131,7 @@ ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk +ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst ad_connect axi_ad9144_dma/m_axis_xfer_req axi_ad9144_fifo/dma_xfer_req ad_connect axi_ad9144_dma/m_axis_aclk axi_ad9144_fifo/dma_clk ad_connect axi_ad9144_dma/m_axis_ready axi_ad9144_fifo/dma_ready From 09be227db912001e0ab840eebb392027725f1ace Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 9 Oct 2015 13:19:09 +0300 Subject: [PATCH 18/19] fmcomms2/zc706pr: Update PR design + Add system_top.v to design + Add pr specific constraints --- projects/fmcomms2/zc706pr/system_bd.tcl | 1 + projects/fmcomms2/zc706pr/system_constr.xdc | 44 +++ projects/fmcomms2/zc706pr/system_project.tcl | 11 +- projects/fmcomms2/zc706pr/system_top.v | 343 +++++++++++++++++++ projects/scripts/adi_project.tcl | 5 +- 5 files changed, 397 insertions(+), 7 deletions(-) create mode 100644 projects/fmcomms2/zc706pr/system_constr.xdc create mode 100644 projects/fmcomms2/zc706pr/system_top.v diff --git a/projects/fmcomms2/zc706pr/system_bd.tcl b/projects/fmcomms2/zc706pr/system_bd.tcl index 07554df73..e4f0c9a3f 100755 --- a/projects/fmcomms2/zc706pr/system_bd.tcl +++ b/projects/fmcomms2/zc706pr/system_bd.tcl @@ -1,3 +1,4 @@ source ../zc706/system_bd.tcl +source ../common/prcfg_bd.tcl diff --git a/projects/fmcomms2/zc706pr/system_constr.xdc b/projects/fmcomms2/zc706pr/system_constr.xdc new file mode 100644 index 000000000..53377ada7 --- /dev/null +++ b/projects/fmcomms2/zc706pr/system_constr.xdc @@ -0,0 +1,44 @@ + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*i_pn_mon* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*input_pipeline_phase* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_adc_ddata_reg*}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg*}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_im_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_re_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_im_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] + diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl index c7a4ba723..b781c51c6 100755 --- a/projects/fmcomms2/zc706pr/system_project.tcl +++ b/projects/fmcomms2/zc706pr/system_project.tcl @@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcomms2_zc706 1 adi_project_synth fmcomms2_zc706 "" \ - [list "../zc706/system_top.v" \ + [list "system_top.v" \ "$ad_hdl_dir/library/prcfg/common/prcfg_bb.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v"] \ [list "../zc706/system_constr.xdc" \ @@ -18,7 +18,9 @@ adi_project_synth fmcomms2_zc706 "default" \ "$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \ "$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \ "$ad_hdl_dir/library/prcfg/default/prcfg_adc.v"] -adi_project_impl fmcomms2_zc706 "default" "../common/prcfg.xdc" +adi_project_impl fmcomms2_zc706 "default" \ + [list "../common/prcfg.xdc" \ + "system_constr.xdc"] adi_project_synth fmcomms2_zc706 "bist" \ [list "../common/prcfg.v" \ @@ -26,7 +28,7 @@ adi_project_synth fmcomms2_zc706 "bist" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/prcfg/bist/prcfg_dac.v" \ "$ad_hdl_dir/library/prcfg/bist/prcfg_adc.v"] -adi_project_impl fmcomms2_zc706 "bist" +adi_project_impl fmcomms2_zc706 "bist" "system_constr.xdc" adi_project_synth fmcomms2_zc706 "qpsk" \ [list "../common/prcfg.v" \ @@ -42,8 +44,7 @@ adi_project_synth fmcomms2_zc706 "qpsk" \ "$ad_hdl_dir/library/prcfg/qpsk/FIR_Decimation.v" \ "$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v" \ "$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v"] -adi_project_impl fmcomms2_zc706 "qpsk" +adi_project_impl fmcomms2_zc706 "qpsk" "system_constr.xdc" adi_project_verify fmcomms2_zc706 - diff --git a/projects/fmcomms2/zc706pr/system_top.v b/projects/fmcomms2/zc706pr/system_top.v new file mode 100644 index 000000000..57d44b383 --- /dev/null +++ b/projects/fmcomms2/zc706pr/system_top.v @@ -0,0 +1,343 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + inout gpio_txnrx; + inout gpio_enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire clk; + wire dma_dac_dunf; + wire core_dac_dunf; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; + wire dma_dac_en; + wire core_dac_en; + wire dma_dac_dvalid; + wire core_dac_dvalid; + + wire dma_adc_ovf; + wire core_adc_ovf; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; + wire dma_adc_dwr; + wire core_adc_dwr; + wire dma_adc_dsync; + wire core_adc_dsync; + wire [31:0] adc_gpio_input; + wire [31:0] adc_gpio_output; + wire [31:0] dac_gpio_input; + wire [31:0] dac_gpio_output; + wire tdd_sync_t; + wire tdd_sync_o; + wire tdd_sync_i; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( + .dio_t ({gpio_t[50:49], gpio_t[46:32]}), + .dio_i ({gpio_o[50:49], gpio_o[46:32]}), + .dio_o ({gpio_i[50:49], gpio_i[46:32]}), + .dio_p ({ gpio_muxout_tx, // 50:50 + gpio_muxout_rx, // 49:49 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); + + // prcfg instance + prcfg i_prcfg ( + .clk(clk), + .adc_gpio_input(adc_gpio_input), + .adc_gpio_output(adc_gpio_output), + .dac_gpio_input(dac_gpio_input), + .dac_gpio_output(dac_gpio_output), + .dma_dac_en(dma_dac_en), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .dma_dac_dvalid(dma_dac_dvalid), + .core_dac_en(core_dac_en), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_dac_dvalid(core_dac_dvalid), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + // pr related ports + .clk(clk), + .dma_dac_en(dma_dac_en), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .dma_dac_dvalid(dma_dac_dvalid), + .core_dac_en(core_dac_en), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_dac_dvalid(core_dac_dvalid), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf), + .up_dac_gpio_in(dac_gpio_output), + .up_adc_gpio_in(adc_gpio_output), + .up_dac_gpio_out(dac_gpio_input), + .up_adc_gpio_out(adc_gpio_input) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index fe1b776c5..1b714ea16 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -1,6 +1,6 @@ -variable p_board -variable p_device +variable p_board +variable p_device variable sys_zynq variable p_prcfg_init variable p_prcfg_list @@ -226,6 +226,7 @@ proc adi_project_impl {project_name prcfg_name {xdc_files ""}} { open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device lock_design -level routing read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp + read_xdc $xdc_files opt_design > $p_prefix.${prcfg_name}_opt.rds place_design > $p_prefix.${prcfg_name}_place.rds route_design > $p_prefix.${prcfg_name}_route.rds From 199227b78c48e1603d9d0cb0b3d0ce5607dc2548 Mon Sep 17 00:00:00 2001 From: Nicholas Pillitteri Date: Tue, 13 Oct 2015 10:19:08 -0400 Subject: [PATCH 19/19] fix fmcjesdadc1_bd ILA warning --- projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index 13d677192..e4aae708a 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -198,15 +198,15 @@ ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {32}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE2_WIDTH {32}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE3_WIDTH {32}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE5_WIDTH {32}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE5_WIDTH {1}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE6_WIDTH {1}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE7_WIDTH {1}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE8_WIDTH {1}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE9_WIDTH {1}] $ila_jesd_rx_mon ad_connect axi_ad9250_gt_rx_clk ila_jesd_rx_mon/CLK ad_connect axi_ad9250_gt_rx_data ila_jesd_rx_mon/PROBE0