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Merge branch 'master' into dev 

Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
main
Istvan Csomortani 2015-11-26 13:38:11 +02:00
parent 667e49fe41 296093ad53
commit 36febf8591
2 changed files with 2 additions and 40 deletions
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40
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -103,46 +103,6 @@ foreach p $dummy_axi_ports {
adi_set_ports_dependency $p "0" adi_set_ports_dependency $p "0"
} }
# These are in the design to keep the Altera tools happy which can't handle
# uni-directional AXI interfaces. The Xilinx tools can and do a better job when
# they know that the interface is uni-directional, so disable the ports.
set dummy_axi_ports [list \
"m_dest_axi_arvalid" \
"m_dest_axi_arready" \
"m_dest_axi_araddr" \
"m_dest_axi_arlen" \
"m_dest_axi_arsize" \
"m_dest_axi_arburst" \
"m_dest_axi_arcache" \
"m_dest_axi_arprot" \
"m_dest_axi_rready" \
"m_dest_axi_rvalid" \
"m_dest_axi_rresp" \
"m_dest_axi_rdata" \
"m_src_axi_awvalid" \
"m_src_axi_awready" \
"m_src_axi_awvalid" \
"m_src_axi_awaddr" \
"m_src_axi_awlen" \
"m_src_axi_awsize" \
"m_src_axi_awburst" \
"m_src_axi_awcache" \
"m_src_axi_awprot" \
"m_src_axi_wvalid" \
"m_src_axi_wready" \
"m_src_axi_wvalid" \
"m_src_axi_wdata" \
"m_src_axi_wstrb" \
"m_src_axi_wlast" \
"m_src_axi_bready" \
"m_src_axi_bvalid" \
"m_src_axi_bresp" \
]
foreach p $dummy_axi_ports {
adi_set_ports_dependency $p "0"
}
adi_add_bus "fifo_wr" "slave" \ adi_add_bus "fifo_wr" "slave" \
"analog.com:interface:fifo_wr_rtl:1.0" \ "analog.com:interface:fifo_wr_rtl:1.0" \
"analog.com:interface:fifo_wr:1.0" \ "analog.com:interface:fifo_wr:1.0" \

2
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -61,6 +61,8 @@ set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd] set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd
set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ] $axi_usdrx1_jesd
set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt