zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

util_dacfifo: Add a bypass option to the FIFO

main
Istvan Csomortani 2016-03-21 14:14:43 +02:00
parent 896c734792
commit 373481360b
2 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
library/util_dacfifo/util_dacfifo.v
View File

@ -55,7 +55,9 @@ module util_dacfifo (
dac_clk, dac_clk,
dac_valid, dac_valid,
dac_data dac_data,
dac_fifo_bypass
); );
// depth of the FIFO // depth of the FIFO
@ -80,6 +82,8 @@ module util_dacfifo (
input dac_valid; input dac_valid;
output [(DATA_WIDTH-1):0] dac_data; output [(DATA_WIDTH-1):0] dac_data;
input dac_fifo_bypass;
// internal registers // internal registers
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
@ -87,10 +91,9 @@ module util_dacfifo (
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0;
reg dma_xfer_req_ff = 1'b0; reg dma_xfer_req_ff = 1'b0;
reg dma_ready = 1'b0; reg dma_ready_d = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
reg [(DATA_WIDTH-1):0] dac_data = 'b0;
// internal wires // internal wires
wire dma_wren; wire dma_wren;
@ -99,10 +102,10 @@ module util_dacfifo (
// write interface // write interface
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin if(dma_rst == 1'b1) begin
dma_ready <= 1'b0; dma_ready_d <= 1'b0;
dma_xfer_req_ff <= 1'b0; dma_xfer_req_ff <= 1'b0;
end else begin end else begin
dma_ready <= 1'b1; // Fifo is always ready dma_ready_d <= 1'b1; // Fifo is always ready
dma_xfer_req_ff <= dma_xfer_req; dma_xfer_req_ff <= dma_xfer_req;
end end
end end
@ -141,10 +144,8 @@ module util_dacfifo (
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
end end
end end
dac_data <= dac_data_s;
end end
// memory instantiation // memory instantiation
ad_mem #( ad_mem #(
@ -159,5 +160,10 @@ module util_dacfifo (
.addrb (dac_raddr), .addrb (dac_raddr),
.doutb (dac_data_s)); .doutb (dac_data_s));
// output logic
assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_d;
endmodule endmodule

2
projects/common/xilinx/sys_dmafifo.tcl
View File

@ -67,6 +67,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
create_bd_pin -dir I -from [expr ($data_width-1)] -to 0 dma_data create_bd_pin -dir I -from [expr ($data_width-1)] -to 0 dma_data
create_bd_pin -dir I dma_xfer_req create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir I dma_xfer_last create_bd_pin -dir I dma_xfer_last
create_bd_pin -dir I dac_fifo_bypass
create_bd_pin -dir I dac_clk create_bd_pin -dir I dac_clk
create_bd_pin -dir I dac_valid create_bd_pin -dir I dac_valid
@ -86,6 +87,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
ad_connect dma_xfer_last util_dacfifo/dma_xfer_last ad_connect dma_xfer_last util_dacfifo/dma_xfer_last
ad_connect dac_valid util_dacfifo/dac_valid ad_connect dac_valid util_dacfifo/dac_valid
ad_connect dac_data util_dacfifo/dac_data ad_connect dac_data util_dacfifo/dac_data
ad_connect dac_fifo_bypass util_dacfifo/dac_fifo_bypass
current_bd_instance $c_instance current_bd_instance $c_instance
} }