zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'hdl_2015_r2' into dev

main
Adrian Costina 2016-02-19 14:15:27 +02:00
parent ce760eb691 0f37dd6424
commit 377461e0d4
28 changed files with 1564 additions and 962 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
library/util_upack/util_upack_dsf.v
View File

@ -91,6 +91,7 @@ module util_upack_dsf (
reg [(M_WIDTH-1):0] dac_data_int = 'd0; reg [(M_WIDTH-1):0] dac_data_int = 'd0;
reg [(M_WIDTH-1):0] dac_dsf_data_int = 'd0; reg [(M_WIDTH-1):0] dac_dsf_data_int = 'd0;
reg [(M_WIDTH-1):0] dac_dsf_data = 'd0; reg [(M_WIDTH-1):0] dac_dsf_data = 'd0;
reg dac_valid_d1 = 'd0;
// internal signals // internal signals
@ -150,15 +151,29 @@ module util_upack_dsf (
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_dmx_valid <= dac_valid & dac_dmx_enable; dac_dmx_valid <= dac_valid & dac_dmx_enable;
if (dac_samples_int_s < NUM_OF_CHANNELS_O) begin dac_valid_d1 <= dac_valid;
dac_dsf_valid <= dac_valid & dac_dmx_enable; if (dac_valid_d1 == 1'b1) begin
if (dac_samples_int_s < NUM_OF_CHANNELS_O) begin
dac_dsf_valid <= dac_valid & dac_dmx_enable;
end else begin
dac_dsf_valid <= 1'b0;
end
if (dac_samples_int_s == 0) begin
dac_dsf_sync <= dac_valid & dac_dmx_enable;
end else begin
dac_dsf_sync <= 1'b0;
end
end else begin end else begin
dac_dsf_valid <= 1'b0; if (dac_samples_int < NUM_OF_CHANNELS_O) begin
end dac_dsf_valid <= dac_valid & dac_dmx_enable;
if (dac_samples_int_s == 0) begin end else begin
dac_dsf_sync <= dac_valid & dac_dmx_enable; dac_dsf_valid <= 1'b0;
end else begin end
dac_dsf_sync <= 1'b0; if (dac_samples_int == 0) begin
dac_dsf_sync <= dac_valid & dac_dmx_enable;
end else begin
dac_dsf_sync <= 1'b0;
end
end end
if (dac_dmx_valid == 1'b1) begin if (dac_dmx_valid == 1'b1) begin
dac_samples_int <= dac_samples_int_s; dac_samples_int <= dac_samples_int_s;

1
projects/ad6676evb/vc707/system_constr.xdc
View File

@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/ad6676evb/zc706/system_constr.xdc
View File

@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

59
projects/arradio/c5soc/system_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element arradio element arradio
{ {
datum _sortIndex datum _sortIndex
@ -49,6 +41,14 @@
type = "String"; type = "String";
} }
} }
element arradio.gpio_s1
{
datum baseAddress
{
value = "36864";
type = "String";
}
}
element arradio.spi_ad9361_spi_control_port element arradio.spi_ad9361_spi_control_port
{ {
datum baseAddress datum baseAddress
@ -233,14 +233,14 @@
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" /> <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" /> <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter> <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
<parameter <parameter
name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH" name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
value="AddressWidth = 18" /> value="AddressWidth = 18" />
<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" /> <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" /> <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
</module> </module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1"> <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="50000000" /> <parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" /> <parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" /> <parameter name="inputClockFrequency" value="0" />
@ -248,7 +248,7 @@
</module> </module>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="arradio.axi_dmac_adc_m_dest_axi" start="arradio.axi_dmac_adc_m_dest_axi"
end="c5soc.sys_mem_interconnect_axi0_s0"> end="c5soc.sys_mem_interconnect_axi0_s0">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -257,7 +257,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="arradio.axi_dmac_dac_m_src_axi" start="arradio.axi_dmac_dac_m_src_axi"
end="c5soc.sys_mem_interconnect_axi1_s0"> end="c5soc.sys_mem_interconnect_axi1_s0">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -266,7 +266,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="c5soc.sys_cpu_interconnect_m0" start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_ad9361_s_axi"> end="arradio.axi_ad9361_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -275,7 +275,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="c5soc.sys_cpu_interconnect_m0" start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_dmac_adc_s_axi"> end="arradio.axi_dmac_adc_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -284,7 +284,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="c5soc.sys_cpu_interconnect_m0" start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_dmac_dac_s_axi"> end="arradio.axi_dmac_dac_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -293,54 +293,63 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.gpio_s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0" start="c5soc.sys_cpu_interconnect_m0"
end="arradio.spi_ad9361_spi_control_port"> end="arradio.spi_ad9361_spi_control_port">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" /> <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection kind="clock" version="15.0" start="sys_clk.clk" end="c5soc.sys_clk" /> <connection kind="clock" version="15.1" start="sys_clk.clk" end="c5soc.sys_clk" />
<connection kind="clock" version="15.0" start="sys_clk.clk" end="arradio.sys_clk" /> <connection kind="clock" version="15.1" start="sys_clk.clk" end="arradio.sys_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="c5soc.mem_clk" start="c5soc.mem_clk"
end="arradio.mem_clk" /> end="arradio.mem_clk" />
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="c5soc.sys_intr" start="c5soc.sys_intr"
end="arradio.axi_dmac_adc_intr"> end="arradio.axi_dmac_adc_intr">
<parameter name="irqNumber" value="2" /> <parameter name="irqNumber" value="2" />
</connection> </connection>
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="c5soc.sys_intr" start="c5soc.sys_intr"
end="arradio.axi_dmac_dac_intr"> end="arradio.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" /> <parameter name="irqNumber" value="1" />
</connection> </connection>
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="c5soc.sys_intr" start="c5soc.sys_intr"
end="arradio.spi_ad9361_irq"> end="arradio.spi_ad9361_irq">
<parameter name="irqNumber" value="0" /> <parameter name="irqNumber" value="0" />
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="c5soc.sys_rst" /> end="c5soc.sys_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="arradio.sys_rst" /> end="arradio.sys_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="c5soc.mem_rst" start="c5soc.mem_rst"
end="arradio.mem_rst" /> end="arradio.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

2
projects/arradio/c5soc/system_project.tcl
View File

@ -5,7 +5,7 @@ source ../../scripts/adi_env.tcl
project_new arradio_c5soc -overwrite project_new arradio_c5soc -overwrite
source "../../common/c5soc/c5soc_system_assign.tcl" source "../../common/c5soc/c5soc_system_assign.tcl"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/c5soc;../../../library/**/*" set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*" set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name QSYS_FILE system_bd.qsys

124
projects/arradio/common/arradio_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element ad9361_clk_bridge element ad9361_clk_bridge
{ {
datum _sortIndex datum _sortIndex
@ -86,6 +78,14 @@
type = "String"; type = "String";
} }
} }
element arradio_bd
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element axi_ad9361 element axi_ad9361
{ {
datum _sortIndex datum _sortIndex
@ -330,7 +330,7 @@
<module <module
name="ad9361_clk_bridge" name="ad9361_clk_bridge"
kind="altera_clock_bridge" kind="altera_clock_bridge"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" /> <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
@ -354,12 +354,12 @@
<parameter name="DMA_2D_TRANSFER" value="0" /> <parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" /> <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" /> <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" /> <parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="0" /> <parameter name="DMA_TYPE_DEST" value="0" />
<parameter name="DMA_TYPE_SRC" value="2" /> <parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" /> <parameter name="FIFO_SIZE" value="4" />
<parameter name="ID" value="0" /> <parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" /> <parameter name="SYNC_TRANSFER_START" value="1" />
</module> </module>
<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1"> <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
<parameter name="ASYNC_CLK_DEST_REQ" value="1" /> <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
@ -371,7 +371,7 @@
<parameter name="DMA_2D_TRANSFER" value="0" /> <parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" /> <parameter name="DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" /> <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" /> <parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="2" /> <parameter name="DMA_TYPE_DEST" value="2" />
<parameter name="DMA_TYPE_SRC" value="0" /> <parameter name="DMA_TYPE_SRC" value="0" />
<parameter name="FIFO_SIZE" value="4" /> <parameter name="FIFO_SIZE" value="4" />
@ -382,7 +382,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="16" /> <parameter name="CHANNEL_DATA_WIDTH" value="16" />
<parameter name="NUM_OF_CHANNELS" value="4" /> <parameter name="NUM_OF_CHANNELS" value="4" />
</module> </module>
<module name="gpio" kind="altera_avalon_pio" version="15.0" enabled="1"> <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" /> <parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" /> <parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" /> <parameter name="captureEdge" value="false" />
@ -396,19 +396,19 @@
<parameter name="simDrivenValue" value="0" /> <parameter name="simDrivenValue" value="0" />
<parameter name="width" value="5" /> <parameter name="width" value="5" />
</module> </module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" /> <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" /> <parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" /> <parameter name="USE_RESET_REQUEST" value="0" />
</module> </module>
<module name="spi_ad9361" kind="altera_avalon_spi" version="15.0" enabled="1"> <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" /> <parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" /> <parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="1" /> <parameter name="clockPolarity" value="1" />
@ -424,84 +424,82 @@
<parameter name="targetClockRate" value="50000000" /> <parameter name="targetClockRate" value="50000000" />
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" /> <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
</module> </module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" /> <parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" /> <parameter name="USE_RESET_REQUEST" value="0" />
</module> </module>
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9361.if_l_clk" start="axi_ad9361.if_l_clk"
end="adc_pack.if_adc_clk" /> end="adc_pack.if_adc_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9361.if_l_clk" start="axi_ad9361.if_l_clk"
end="dac_upack.if_dac_clk" /> end="dac_upack.if_dac_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9361.if_l_clk" start="axi_ad9361.if_l_clk"
end="axi_dmac_dac.if_fifo_rd_clk" /> end="axi_dmac_dac.if_fifo_rd_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9361.if_l_clk" start="axi_ad9361.if_l_clk"
end="axi_dmac_adc.if_fifo_wr_clk" /> end="axi_dmac_adc.if_fifo_wr_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9361.if_l_clk" start="axi_ad9361.if_l_clk"
end="ad9361_clk_bridge.in_clk" /> end="ad9361_clk_bridge.in_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="spi_ad9361.clk" /> end="spi_ad9361.clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" /> <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="gpio.clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9361.delay_clock" /> end="axi_ad9361.delay_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_dmac_adc.m_dest_axi_clock" /> end="axi_dmac_adc.m_dest_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_dmac_dac.m_src_axi_clock" /> end="axi_dmac_dac.m_src_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9361.s_axi_clock" /> end="axi_ad9361.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_dmac_adc.s_axi_clock" /> end="axi_dmac_adc.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_dmac_dac.s_axi_clock" /> end="axi_dmac_dac.s_axi_clock" />
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="dac_upack.fifo_ch_0" start="dac_upack.fifo_ch_0"
end="axi_ad9361.fifo_ch_0_out"> end="axi_ad9361.fifo_ch_0_out">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -512,7 +510,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_0_in" start="axi_ad9361.fifo_ch_0_in"
end="adc_pack.fifo_ch_0"> end="adc_pack.fifo_ch_0">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -523,7 +521,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_1_in" start="axi_ad9361.fifo_ch_1_in"
end="adc_pack.fifo_ch_1"> end="adc_pack.fifo_ch_1">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -534,7 +532,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_1_out" start="axi_ad9361.fifo_ch_1_out"
end="dac_upack.fifo_ch_1"> end="dac_upack.fifo_ch_1">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -545,7 +543,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_2_in" start="axi_ad9361.fifo_ch_2_in"
end="adc_pack.fifo_ch_2"> end="adc_pack.fifo_ch_2">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -556,7 +554,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_2_out" start="axi_ad9361.fifo_ch_2_out"
end="dac_upack.fifo_ch_2"> end="dac_upack.fifo_ch_2">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -567,7 +565,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_3_in" start="axi_ad9361.fifo_ch_3_in"
end="adc_pack.fifo_ch_3"> end="adc_pack.fifo_ch_3">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -578,7 +576,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9361.fifo_ch_3_out" start="axi_ad9361.fifo_ch_3_out"
end="dac_upack.fifo_ch_3"> end="dac_upack.fifo_ch_3">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -589,7 +587,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="adc_pack.if_adc_data" start="adc_pack.if_adc_data"
end="axi_dmac_adc.if_fifo_wr_din"> end="axi_dmac_adc.if_fifo_wr_din">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -600,7 +598,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="adc_pack.if_adc_sync" start="adc_pack.if_adc_sync"
end="axi_dmac_adc.if_fifo_wr_sync"> end="axi_dmac_adc.if_fifo_wr_sync">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -611,7 +609,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="adc_pack.if_adc_valid" start="adc_pack.if_adc_valid"
end="axi_dmac_adc.if_fifo_wr_en"> end="axi_dmac_adc.if_fifo_wr_en">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -622,7 +620,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="dac_upack.if_dac_data" start="dac_upack.if_dac_data"
end="axi_dmac_dac.if_fifo_rd_dout"> end="axi_dmac_dac.if_fifo_rd_dout">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -633,7 +631,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="dac_upack.if_dma_xfer_in" start="dac_upack.if_dma_xfer_in"
end="axi_dmac_dac.if_fifo_rd_xfer_req"> end="axi_dmac_dac.if_fifo_rd_xfer_req">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -644,7 +642,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_dac.if_fifo_rd_en" start="axi_dmac_dac.if_fifo_rd_en"
end="dac_upack.if_dac_valid"> end="dac_upack.if_dac_valid">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -655,7 +653,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_dac.if_fifo_rd_underflow" start="axi_dmac_dac.if_fifo_rd_underflow"
end="axi_ad9361.if_dac_dunf"> end="axi_ad9361.if_dac_dunf">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -666,7 +664,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_adc.if_fifo_wr_overflow" start="axi_dmac_adc.if_fifo_wr_overflow"
end="axi_ad9361.if_adc_dovf"> end="axi_ad9361.if_adc_dovf">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -677,52 +675,52 @@
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_ad9361.if_rst" start="axi_ad9361.if_rst"
end="adc_pack.if_adc_rst" /> end="adc_pack.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="adc_pack.if_adc_rst" /> end="adc_pack.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="adc_pack.if_adc_rst" /> end="adc_pack.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_dmac_adc.m_dest_axi_reset" /> end="axi_dmac_adc.m_dest_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_dmac_dac.m_src_axi_reset" /> end="axi_dmac_dac.m_src_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="spi_ad9361.reset" /> end="spi_ad9361.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="gpio.reset" /> end="gpio.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9361.s_axi_reset" /> end="axi_ad9361.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_dmac_adc.s_axi_reset" /> end="axi_dmac_adc.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_dmac_dac.s_axi_reset" /> end="axi_dmac_dac.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

546
projects/common/a10gx/a10gx_system_bd.qsys
View File

File diff suppressed because one or more lines are too long

942
projects/common/a5gt/a5gt_system_bd.qsys
View File

File diff suppressed because one or more lines are too long

197
projects/common/c5soc/c5soc_system_bd.qsys
View File

File diff suppressed because one or more lines are too long

44
projects/daq2/a10gx/system_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element a10gx_base element a10gx_base
{ {
datum _sortIndex datum _sortIndex
@ -445,11 +437,11 @@
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter> <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
</module> </module>
<module name="daq2" kind="daq2_bd" version="1.0" enabled="1"> <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter> <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter <parameter
name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH" name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
value="AddressWidth = 29" /> value="AddressWidth = 29" />
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter> <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter <parameter
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH" name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
value="AddressWidth = 29" /> value="AddressWidth = 29" />
@ -471,7 +463,7 @@
<parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" /> <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" /> <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
</module> </module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1"> <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" /> <parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" /> <parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" /> <parameter name="inputClockFrequency" value="0" />
@ -479,7 +471,7 @@
</module> </module>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="daq2.axi_ad9144_dma_m_axi" start="daq2.axi_ad9144_dma_m_axi"
end="a10gx_base.sys_mem_s_avl"> end="a10gx_base.sys_mem_s_avl">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -488,7 +480,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="daq2.axi_ad9680_dma_m_axi" start="daq2.axi_ad9680_dma_m_axi"
end="a10gx_base.sys_mem_s_avl"> end="a10gx_base.sys_mem_s_avl">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -497,7 +489,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a10gx_base.sys_cpu_m_avl" start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9144_core_s_axi"> end="daq2.axi_ad9144_core_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -506,7 +498,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a10gx_base.sys_cpu_m_avl" start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9144_dma_s_axi"> end="daq2.axi_ad9144_dma_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -515,7 +507,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a10gx_base.sys_cpu_m_avl" start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9680_core_s_axi"> end="daq2.axi_ad9680_core_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -524,7 +516,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a10gx_base.sys_cpu_m_avl" start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9680_dma_s_axi"> end="daq2.axi_ad9680_dma_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -533,7 +525,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a10gx_base.sys_cpu_m_avl" start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_jesd_xcvr_s_axi"> end="daq2.axi_jesd_xcvr_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -542,42 +534,42 @@
</connection> </connection>
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.clk" start="sys_clk.clk"
end="a10gx_base.sys_clk" /> end="a10gx_base.sys_clk" />
<connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" /> <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="a10gx_base.mem_clk" start="a10gx_base.mem_clk"
end="daq2.mem_clk" /> end="daq2.mem_clk" />
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="a10gx_base.sys_intr" start="a10gx_base.sys_intr"
end="daq2.axi_ad9144_dma_intr"> end="daq2.axi_ad9144_dma_intr">
<parameter name="irqNumber" value="1" /> <parameter name="irqNumber" value="1" />
</connection> </connection>
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="a10gx_base.sys_intr" start="a10gx_base.sys_intr"
end="daq2.axi_ad9680_dma_intr"> end="daq2.axi_ad9680_dma_intr">
<parameter name="irqNumber" value="0" /> <parameter name="irqNumber" value="0" />
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="a10gx_base.sys_rst" /> end="a10gx_base.sys_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="daq2.sys_rst" /> end="daq2.sys_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="a10gx_base.mem_rst" start="a10gx_base.mem_rst"
end="daq2.mem_rst" /> end="daq2.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

2
projects/daq2/a10gx/system_constr.sdc
View File

@ -14,3 +14,5 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \ i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}] i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]

222
projects/daq2/common/daq2_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element ad9680_adcfifo element ad9680_adcfifo
{ {
datum _sortIndex datum _sortIndex
@ -882,24 +874,24 @@
<parameter name="RX_NUM_OF_LANES" value="4" /> <parameter name="RX_NUM_OF_LANES" value="4" />
<parameter name="TX_NUM_OF_LANES" value="4" /> <parameter name="TX_NUM_OF_LANES" value="4" />
</module> </module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="125000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" /> <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="USE_RESET_REQUEST" value="0" /> <parameter name="USE_RESET_REQUEST" value="0" />
</module> </module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="100000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
@ -914,7 +906,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="64" /> <parameter name="CHANNEL_DATA_WIDTH" value="64" />
<parameter name="NUM_OF_CHANNELS" value="2" /> <parameter name="NUM_OF_CHANNELS" value="2" />
</module> </module>
<module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1"> <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
<parameter name="ADJCNT" value="0" /> <parameter name="ADJCNT" value="0" />
<parameter name="ADJDIR" value="0" /> <parameter name="ADJDIR" value="0" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" /> <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
@ -927,6 +919,13 @@
<parameter name="DID" value="0" /> <parameter name="DID" value="0" />
<parameter name="DLB_TEST" value="0" /> <parameter name="DLB_TEST" value="0" />
<parameter name="ECC_EN" value="0" /> <parameter name="ECC_EN" value="0" />
<parameter name="ED_DEV_KIT" value="NONE" />
<parameter name="ED_FILESET_SIM" value="false" />
<parameter name="ED_FILESET_SYNTH" value="false" />
<parameter name="ED_GENERIC_5SERIES" value="No" />
<parameter name="ED_GENERIC_A10" value="No" />
<parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
<parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
<parameter name="GUI_CFG_F" value="1" /> <parameter name="GUI_CFG_F" value="1" />
<parameter name="GUI_EN_CFG_F" value="true" /> <parameter name="GUI_EN_CFG_F" value="true" />
<parameter name="HD" value="1" /> <parameter name="HD" value="1" />
@ -973,7 +972,7 @@
<module <module
name="xcvr_rst_cntrl" name="xcvr_rst_cntrl"
kind="altera_xcvr_reset_control" kind="altera_xcvr_reset_control"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="CHANNELS" value="4" /> <parameter name="CHANNELS" value="4" />
<parameter name="PLLS" value="1" /> <parameter name="PLLS" value="1" />
@ -990,6 +989,7 @@
<parameter name="T_PLL_POWERDOWN" value="1000" /> <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" /> <parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" /> <parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" /> <parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria 10" /> <parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="1" /> <parameter name="gui_pll_cal_busy" value="1" />
@ -997,7 +997,7 @@
<parameter name="gui_split_interfaces" value="0" /> <parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="0" /> <parameter name="gui_tx_auto_reset" value="0" />
</module> </module>
<module name="xcvr_rx_pll" kind="altera_iopll" version="15.0" enabled="1"> <module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
<parameter name="gui_active_clk" value="false" /> <parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_duty_cycle0" value="50.0" /> <parameter name="gui_actual_duty_cycle0" value="50.0" />
<parameter name="gui_actual_duty_cycle1" value="50.0" /> <parameter name="gui_actual_duty_cycle1" value="50.0" />
@ -1172,7 +1172,7 @@
<parameter name="gui_en_adv_params" value="false" /> <parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" /> <parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_extclkout_ports" value="false" /> <parameter name="gui_en_extclkout_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="false" /> <parameter name="gui_en_lvds_ports" value="Disabled" />
<parameter name="gui_en_phout_ports" value="false" /> <parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" /> <parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" /> <parameter name="gui_enable_cascade_in" value="false" />
@ -1272,7 +1272,9 @@
<parameter name="gui_reference_clock_frequency" value="500.0" /> <parameter name="gui_reference_clock_frequency" value="500.0" />
<parameter name="gui_switchover_delay" value="0" /> <parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter> <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" /> <parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" /> <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_family" value="Arria 10" /> <parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" /> <parameter name="system_info_device_speed_grade" value="2" />
@ -1281,7 +1283,7 @@
<module <module
name="xcvr_rx_ref_clk" name="xcvr_rx_ref_clk"
kind="altera_clock_bridge" kind="altera_clock_bridge"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="500000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@ -1290,7 +1292,7 @@
<module <module
name="xcvr_tx_lane_pll" name="xcvr_tx_lane_pll"
kind="altera_xcvr_atx_pll_a10" kind="altera_xcvr_atx_pll_a10"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="base_device" value="NIGHTFURY5ES2" /> <parameter name="base_device" value="NIGHTFURY5ES2" />
<parameter name="bw_sel" value="medium" /> <parameter name="bw_sel" value="medium" />
@ -1298,6 +1300,7 @@
<parameter name="device_family" value="Arria 10" /> <parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" /> <parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" /> <parameter name="enable_8G_path" value="1" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_atx_to_fpll_cascade_out" value="0" /> <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="1" /> <parameter name="enable_bonding_clks" value="1" />
<parameter name="enable_cascade_out" value="0" /> <parameter name="enable_cascade_out" value="0" />
@ -1322,6 +1325,7 @@
<parameter name="primary_pll_buffer">GX clock output buffer</parameter> <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" /> <parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" /> <parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter> <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" /> <parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" /> <parameter name="rcfg_jtag_enable" value="0" />
@ -1331,6 +1335,7 @@
<parameter name="rcfg_param_vals2" value="" /> <parameter name="rcfg_param_vals2" value="" />
<parameter name="rcfg_profile_cnt" value="2" /> <parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_select" value="1" /> <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" /> <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" /> <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" /> <parameter name="refclk_cnt" value="1" />
@ -1344,6 +1349,7 @@
<parameter name="set_hip_cal_en" value="0" /> <parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" /> <parameter name="set_k_counter" value="1" />
<parameter name="set_l_cascade_counter" value="4" /> <parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="4" /> <parameter name="set_l_counter" value="4" />
<parameter name="set_m_counter" value="50" /> <parameter name="set_m_counter" value="50" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" /> <parameter name="set_manual_reference_clock_frequency" value="100.0" />
@ -1354,7 +1360,7 @@
<parameter name="support_mode" value="user_mode" /> <parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" /> <parameter name="test_mode" value="0" />
</module> </module>
<module name="xcvr_tx_pll" kind="altera_iopll" version="15.0" enabled="1"> <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
<parameter name="gui_active_clk" value="false" /> <parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_duty_cycle0" value="50.0" /> <parameter name="gui_actual_duty_cycle0" value="50.0" />
<parameter name="gui_actual_duty_cycle1" value="50.0" /> <parameter name="gui_actual_duty_cycle1" value="50.0" />
@ -1529,7 +1535,7 @@
<parameter name="gui_en_adv_params" value="false" /> <parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" /> <parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_extclkout_ports" value="false" /> <parameter name="gui_en_extclkout_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="false" /> <parameter name="gui_en_lvds_ports" value="Disabled" />
<parameter name="gui_en_phout_ports" value="false" /> <parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" /> <parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" /> <parameter name="gui_enable_cascade_in" value="false" />
@ -1629,7 +1635,9 @@
<parameter name="gui_reference_clock_frequency" value="500.0" /> <parameter name="gui_reference_clock_frequency" value="500.0" />
<parameter name="gui_switchover_delay" value="0" /> <parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter> <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" /> <parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" /> <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_family" value="Arria 10" /> <parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" /> <parameter name="system_info_device_speed_grade" value="2" />
@ -1638,7 +1646,7 @@
<module <module
name="xcvr_tx_ref_clk" name="xcvr_tx_ref_clk"
kind="altera_clock_bridge" kind="altera_clock_bridge"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="500000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@ -1646,149 +1654,149 @@
</module> </module>
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_tx_ip_avl" start="axi_jesd_xcvr.if_tx_ip_avl"
end="xcvr_core.jesd204_tx_link" /> end="xcvr_core.jesd204_tx_link" />
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="15.0" version="15.1"
start="xcvr_core.jesd204_rx_link" start="xcvr_core.jesd204_rx_link"
end="axi_jesd_xcvr.if_rx_ip_avl" /> end="axi_jesd_xcvr.if_rx_ip_avl" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" /> <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" /> <connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="xcvr_rst_cntrl.clock" /> end="xcvr_rst_cntrl.clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="ad9680_adcfifo.if_dma_clk" /> end="ad9680_adcfifo.if_dma_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_ad9680_dma.if_s_axis_aclk" /> end="axi_ad9680_dma.if_s_axis_aclk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="xcvr_core.jesd204_rx_avs_clk" /> end="xcvr_core.jesd204_rx_avs_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="xcvr_core.jesd204_tx_avs_clk" /> end="xcvr_core.jesd204_tx_avs_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_ad9680_dma.m_dest_axi_clock" /> end="axi_ad9680_dma.m_dest_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_ad9144_dma.m_src_axi_clock" /> end="axi_ad9144_dma.m_src_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_ref_clk.out_clk" start="xcvr_tx_ref_clk.out_clk"
end="xcvr_tx_lane_pll.pll_refclk0" /> end="xcvr_tx_lane_pll.pll_refclk0" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_ref_clk.out_clk" start="xcvr_tx_ref_clk.out_clk"
end="xcvr_tx_pll.refclk" /> end="xcvr_tx_pll.refclk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_ref_clk.out_clk" start="xcvr_rx_ref_clk.out_clk"
end="xcvr_rx_pll.refclk" /> end="xcvr_rx_pll.refclk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_ref_clk.out_clk" start="xcvr_rx_ref_clk.out_clk"
end="xcvr_core.rx_pll_ref_clk" /> end="xcvr_core.rx_pll_ref_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9680_dma.s_axi_clock" /> end="axi_ad9680_dma.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9680_core.s_axi_clock" /> end="axi_ad9680_core.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9144_core.s_axi_clock" /> end="axi_ad9144_core.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_jesd_xcvr.s_axi_clock" /> end="axi_jesd_xcvr.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9144_dma.s_axi_clock" /> end="axi_ad9144_dma.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="util_cpack_0.if_adc_clk" /> end="util_cpack_0.if_adc_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="ad9680_adcfifo.if_adc_clk" /> end="ad9680_adcfifo.if_adc_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_pll.outclk0" start="xcvr_tx_pll.outclk0"
end="util_upack_0.if_dac_clk" /> end="util_upack_0.if_dac_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_pll.outclk0" start="xcvr_tx_pll.outclk0"
end="axi_ad9144_dma.if_fifo_rd_clk" /> end="axi_ad9144_dma.if_fifo_rd_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_ad9680_core.if_rx_clk" /> end="axi_ad9680_core.if_rx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_rx_clk" /> end="axi_jesd_xcvr.if_rx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_pll.outclk0" start="xcvr_tx_pll.outclk0"
end="axi_ad9144_core.if_tx_clk" /> end="axi_ad9144_core.if_tx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_pll.outclk0" start="xcvr_tx_pll.outclk0"
end="axi_jesd_xcvr.if_tx_clk" /> end="axi_jesd_xcvr.if_tx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="xcvr_core.rxlink_clk" /> end="xcvr_core.rxlink_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_tx_pll.outclk0" start="xcvr_tx_pll.outclk0"
end="xcvr_core.txlink_clk" /> end="xcvr_core.txlink_clk" />
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.alldev_lane_aligned" start="xcvr_core.alldev_lane_aligned"
end="xcvr_core.dev_lane_aligned"> end="xcvr_core.dev_lane_aligned">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1799,7 +1807,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9680_core.fifo_ch_0" start="axi_ad9680_core.fifo_ch_0"
end="util_cpack_0.fifo_ch_0"> end="util_cpack_0.fifo_ch_0">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1810,7 +1818,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_0.fifo_ch_1" start="util_cpack_0.fifo_ch_1"
end="axi_ad9680_core.fifo_ch_1"> end="axi_ad9680_core.fifo_ch_1">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1821,7 +1829,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_0.if_adc_data" start="util_cpack_0.if_adc_data"
end="ad9680_adcfifo.if_adc_wdata"> end="ad9680_adcfifo.if_adc_wdata">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1832,7 +1840,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_0.if_adc_valid" start="util_cpack_0.if_adc_valid"
end="ad9680_adcfifo.if_adc_wr"> end="ad9680_adcfifo.if_adc_wr">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1843,7 +1851,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_upack_0.if_dac_valid" start="util_upack_0.if_dac_valid"
end="axi_ad9144_dma.if_fifo_rd_en"> end="axi_ad9144_dma.if_fifo_rd_en">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1854,7 +1862,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="ad9680_adcfifo.if_dma_wdata" start="ad9680_adcfifo.if_dma_wdata"
end="axi_ad9680_dma.if_s_axis_data"> end="axi_ad9680_dma.if_s_axis_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1865,7 +1873,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="ad9680_adcfifo.if_dma_wr" start="ad9680_adcfifo.if_dma_wr"
end="axi_ad9680_dma.if_s_axis_valid"> end="axi_ad9680_dma.if_s_axis_valid">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1876,7 +1884,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="ad9680_adcfifo.if_dma_wready" start="ad9680_adcfifo.if_dma_wready"
end="axi_ad9680_dma.if_s_axis_ready"> end="axi_ad9680_dma.if_s_axis_ready">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1887,7 +1895,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="ad9680_adcfifo.if_dma_xfer_req" start="ad9680_adcfifo.if_dma_xfer_req"
end="axi_ad9680_dma.if_s_axis_xfer_req"> end="axi_ad9680_dma.if_s_axis_xfer_req">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1898,7 +1906,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9144_dma.if_fifo_rd_dout" start="axi_ad9144_dma.if_fifo_rd_dout"
end="util_upack_0.if_dac_data"> end="util_upack_0.if_dac_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1909,7 +1917,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9680_core.if_rx_data" start="axi_ad9680_core.if_rx_data"
end="axi_jesd_xcvr.if_rx_data"> end="axi_jesd_xcvr.if_rx_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1920,7 +1928,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sof" start="axi_jesd_xcvr.if_rx_ip_sof"
end="xcvr_core.rx_sof"> end="xcvr_core.rx_sof">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1931,7 +1939,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sync" start="axi_jesd_xcvr.if_rx_ip_sync"
end="xcvr_core.rx_dev_sync_n"> end="xcvr_core.rx_dev_sync_n">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1942,7 +1950,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sysref" start="axi_jesd_xcvr.if_rx_ip_sysref"
end="xcvr_core.rx_sysref"> end="xcvr_core.rx_sysref">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1953,7 +1961,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ready" start="axi_jesd_xcvr.if_rx_ready"
end="xcvr_rst_cntrl.rx_ready"> end="xcvr_rst_cntrl.rx_ready">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1964,7 +1972,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_tx_data" start="axi_jesd_xcvr.if_tx_data"
end="axi_ad9144_core.if_tx_data"> end="axi_ad9144_core.if_tx_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1975,7 +1983,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_tx_ip_sysref" start="axi_jesd_xcvr.if_tx_ip_sysref"
end="xcvr_core.tx_sysref"> end="xcvr_core.tx_sysref">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1986,7 +1994,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_tx_ready" start="axi_jesd_xcvr.if_tx_ready"
end="xcvr_rst_cntrl.tx_ready"> end="xcvr_rst_cntrl.tx_ready">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1997,7 +2005,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.pll_cal_busy" start="xcvr_rst_cntrl.pll_cal_busy"
end="xcvr_tx_lane_pll.pll_cal_busy"> end="xcvr_tx_lane_pll.pll_cal_busy">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2008,7 +2016,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.pll_locked" start="xcvr_tx_lane_pll.pll_locked"
end="xcvr_rst_cntrl.pll_locked"> end="xcvr_rst_cntrl.pll_locked">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2019,7 +2027,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.pll_powerdown" start="xcvr_tx_lane_pll.pll_powerdown"
end="xcvr_rst_cntrl.pll_powerdown"> end="xcvr_rst_cntrl.pll_powerdown">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2030,7 +2038,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.rx_analogreset" start="xcvr_rst_cntrl.rx_analogreset"
end="xcvr_core.rx_analogreset"> end="xcvr_core.rx_analogreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2041,7 +2049,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.rx_cal_busy" start="xcvr_core.rx_cal_busy"
end="xcvr_rst_cntrl.rx_cal_busy"> end="xcvr_rst_cntrl.rx_cal_busy">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2052,7 +2060,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.rx_digitalreset" start="xcvr_core.rx_digitalreset"
end="xcvr_rst_cntrl.rx_digitalreset"> end="xcvr_rst_cntrl.rx_digitalreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2063,7 +2071,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.rx_is_lockedtodata" start="xcvr_rst_cntrl.rx_is_lockedtodata"
end="xcvr_core.rx_islockedtodata"> end="xcvr_core.rx_islockedtodata">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2074,7 +2082,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.sync_n" start="xcvr_core.sync_n"
end="axi_jesd_xcvr.if_tx_ip_sync"> end="axi_jesd_xcvr.if_tx_ip_sync">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2085,7 +2093,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.tx_analogreset" start="xcvr_rst_cntrl.tx_analogreset"
end="xcvr_core.tx_analogreset"> end="xcvr_core.tx_analogreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2096,7 +2104,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.tx_cal_busy" start="xcvr_rst_cntrl.tx_cal_busy"
end="xcvr_core.tx_cal_busy"> end="xcvr_core.tx_cal_busy">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2107,7 +2115,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.tx_dev_sync_n" start="xcvr_core.tx_dev_sync_n"
end="xcvr_core.mdev_sync_n"> end="xcvr_core.mdev_sync_n">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2118,7 +2126,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.tx_digitalreset" start="xcvr_rst_cntrl.tx_digitalreset"
end="xcvr_core.tx_digitalreset"> end="xcvr_core.tx_digitalreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -2129,127 +2137,127 @@
</connection> </connection>
<connection <connection
kind="hssi_serial_clock" kind="hssi_serial_clock"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk" start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch0" /> end="xcvr_core.tx_serial_clk0_ch0" />
<connection <connection
kind="hssi_serial_clock" kind="hssi_serial_clock"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk" start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch1" /> end="xcvr_core.tx_serial_clk0_ch1" />
<connection <connection
kind="hssi_serial_clock" kind="hssi_serial_clock"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk" start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch2" /> end="xcvr_core.tx_serial_clk0_ch2" />
<connection <connection
kind="hssi_serial_clock" kind="hssi_serial_clock"
version="15.0" version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk" start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch3" /> end="xcvr_core.tx_serial_clk0_ch3" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rst" start="axi_jesd_xcvr.if_rst"
end="xcvr_tx_pll.reset" /> end="xcvr_tx_pll.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rst" start="axi_jesd_xcvr.if_rst"
end="xcvr_rx_pll.reset" /> end="xcvr_rx_pll.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rst" start="axi_jesd_xcvr.if_rst"
end="xcvr_rst_cntrl.reset" /> end="xcvr_rst_cntrl.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_rstn" start="axi_jesd_xcvr.if_rx_rstn"
end="xcvr_core.rxlink_rst_n" /> end="xcvr_core.rxlink_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_tx_rstn" start="axi_jesd_xcvr.if_tx_rstn"
end="xcvr_core.txlink_rst_n" /> end="xcvr_core.txlink_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="util_cpack_0.if_adc_rst" /> end="util_cpack_0.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="util_cpack_0.if_adc_rst" /> end="util_cpack_0.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="ad9680_adcfifo.if_adc_rst" /> end="ad9680_adcfifo.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="ad9680_adcfifo.if_adc_rst" /> end="ad9680_adcfifo.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_core.jesd204_rx_avs_rst_n" /> end="xcvr_core.jesd204_rx_avs_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_core.jesd204_tx_avs_rst_n" /> end="xcvr_core.jesd204_tx_avs_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_ad9680_dma.m_dest_axi_reset" /> end="axi_ad9680_dma.m_dest_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_ad9144_dma.m_src_axi_reset" /> end="axi_ad9144_dma.m_src_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" /> end="xcvr_rst_cntrl.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_tx_pll.reset" /> end="xcvr_tx_pll.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_rx_pll.reset" /> end="xcvr_rx_pll.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_jesd_xcvr.s_axi_reset" /> end="axi_jesd_xcvr.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9144_core.s_axi_reset" /> end="axi_ad9144_core.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9680_core.s_axi_reset" /> end="axi_ad9680_core.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9680_dma.s_axi_reset" /> end="axi_ad9680_dma.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9144_dma.s_axi_reset" /> end="axi_ad9144_dma.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

6
projects/daq2/kc705/system_constr.xdc
View File

@ -56,7 +56,5 @@ set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_po
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK] create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

5
projects/daq2/vc707/system_constr.xdc
View File

@ -56,7 +56,6 @@ set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK] create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/fmcadc2/vc707/system_constr.xdc
View File

@ -38,3 +38,4 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd]
# clocks # clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

2
projects/fmcadc2/zc706/system_constr.xdc
View File

@ -38,4 +38,4 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd]
# clocks # clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

90
projects/fmcjesdadc1/a5gt/system_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element a5gt_base element a5gt_base
{ {
datum _sortIndex datum _sortIndex
@ -73,6 +65,14 @@
type = "String"; type = "String";
} }
} }
element fmcjesdadc1.axi_jesd204_rx_avs
{
datum baseAddress
{
value = "262144";
type = "String";
}
}
element fmcjesdadc1.axi_jesd_xcvr_s_axi element fmcjesdadc1.axi_jesd_xcvr_s_axi
{ {
datum baseAddress datum baseAddress
@ -169,6 +169,22 @@
type = "String"; type = "String";
} }
} }
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" /> <parameter name="clockCrossingAdapter" value="FIFO" />
@ -308,26 +324,26 @@
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5gt_base</parameter> <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5gt_base</parameter>
</module> </module>
<module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1"> <module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter> <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" /> <parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter> <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" /> <parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
<parameter name="AUTO_CPU_CLK_CLOCK_DOMAIN" value="9" />
<parameter name="AUTO_CPU_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_CPU_CLK_RESET_DOMAIN" value="9" />
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" /> <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" /> <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" /> <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="AUTO_GENERATION_ID" value="0" /> <parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="9" /> <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="10" />
<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="100000000" /> <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="9" /> <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="10" />
<parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="6" /> <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="6" />
<parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" /> <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="6" /> <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="6" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="7" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="7" />
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter> <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
</module> </module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1"> <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" /> <parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" /> <parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" /> <parameter name="inputClockFrequency" value="0" />
@ -335,7 +351,7 @@
</module> </module>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="fmcjesdadc1.axi_dmac_0_m_axi" start="fmcjesdadc1.axi_dmac_0_m_axi"
end="a5gt_base.sys_mem_interconnect_s0"> end="a5gt_base.sys_mem_interconnect_s0">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -344,7 +360,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="fmcjesdadc1.axi_dmac_1_m_axi" start="fmcjesdadc1.axi_dmac_1_m_axi"
end="a5gt_base.sys_mem_interconnect_s0"> end="a5gt_base.sys_mem_interconnect_s0">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -353,7 +369,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0" start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_ad9250_0_s_axi"> end="fmcjesdadc1.axi_ad9250_0_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -362,7 +378,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0" start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_ad9250_1_s_axi"> end="fmcjesdadc1.axi_ad9250_1_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -371,7 +387,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0" start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_dmac_0_s_axi"> end="fmcjesdadc1.axi_dmac_0_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -380,7 +396,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0" start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_dmac_1_s_axi"> end="fmcjesdadc1.axi_dmac_1_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -389,7 +405,7 @@
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
version="15.0" version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0" start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_jesd_xcvr_s_axi"> end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
@ -398,46 +414,46 @@
</connection> </connection>
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.clk" start="sys_clk.clk"
end="a5gt_base.sys_clk" /> end="a5gt_base.sys_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.clk" start="a5gt_base.cpu_clk"
end="fmcjesdadc1.sys_clk" /> end="fmcjesdadc1.cpu_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="a5gt_base.mem_clk" start="a5gt_base.mem_clk"
end="fmcjesdadc1.mem_clk" /> end="fmcjesdadc1.mem_clk" />
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="a5gt_base.sys_intr" start="a5gt_base.sys_intr"
end="fmcjesdadc1.axi_dmac_0_intr"> end="fmcjesdadc1.axi_dmac_0_intr">
<parameter name="irqNumber" value="1" /> <parameter name="irqNumber" value="1" />
</connection> </connection>
<connection <connection
kind="interrupt" kind="interrupt"
version="15.0" version="15.1"
start="a5gt_base.sys_intr" start="a5gt_base.sys_intr"
end="fmcjesdadc1.axi_dmac_1_intr"> end="fmcjesdadc1.axi_dmac_1_intr">
<parameter name="irqNumber" value="0" /> <parameter name="irqNumber" value="0" />
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="sys_clk.clk_reset"
end="a5gt_base.sys_rst" /> end="a5gt_base.sys_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_clk.clk_reset" start="a5gt_base.cpu_rst"
end="fmcjesdadc1.sys_rst" /> end="fmcjesdadc1.cpu_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="a5gt_base.mem_rst" start="a5gt_base.mem_rst"
end="fmcjesdadc1.mem_rst" /> end="fmcjesdadc1.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

7
projects/fmcjesdadc1/a5gt/system_constr.sdc
View File

@ -9,6 +9,9 @@ derive_clock_uncertainty
set_clock_groups -exclusive \ set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_clock_groups -asynchronous \
-group {ref_clk_250mhz} \
-group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]

4
projects/fmcjesdadc1/a5gt/system_project.tcl
View File

@ -5,8 +5,8 @@ source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite project_new fmcjesdadc1_a5gt -overwrite
source "../../common/a5gt/a5gt_system_assign.tcl" source "../../common/a5gt/a5gt_system_assign.tcl"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5gt;../../../library/**/*" set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5gt/;../../../library/**/*" set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v" set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"

216
projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element axi_ad9250_0 element axi_ad9250_0
{ {
datum _sortIndex datum _sortIndex
@ -434,11 +426,18 @@
internal="axi_dmac_1.s_axi" internal="axi_dmac_1.s_axi"
type="axi4lite" type="axi4lite"
dir="end" /> dir="end" />
<interface
name="axi_jesd204_rx_avs"
internal="xcvr_core.jesd204_rx_avs"
type="avalon"
dir="end" />
<interface <interface
name="axi_jesd_xcvr_s_axi" name="axi_jesd_xcvr_s_axi"
internal="axi_jesd_xcvr.s_axi" internal="axi_jesd_xcvr.s_axi"
type="axi4lite" type="axi4lite"
dir="end" /> dir="end" />
<interface name="cpu_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface name="cpu_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
<interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" /> <interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
<interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" /> <interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
<interface <interface
@ -457,8 +456,6 @@
internal="axi_jesd_xcvr.if_rx_ext_sysref_out" internal="axi_jesd_xcvr.if_rx_ext_sysref_out"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
<interface name="tx_ref_clk" internal="axi_jesd_xcvr.if_tx_ref_clk" /> <interface name="tx_ref_clk" internal="axi_jesd_xcvr.if_tx_ref_clk" />
<module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1"> <module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1">
<parameter name="DEVICE_TYPE" value="0" /> <parameter name="DEVICE_TYPE" value="0" />
@ -474,14 +471,14 @@
<parameter name="ASYNC_CLK_SRC_DEST" value="1" /> <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
<parameter name="AXI_SLICE_DEST" value="0" /> <parameter name="AXI_SLICE_DEST" value="0" />
<parameter name="AXI_SLICE_SRC" value="0" /> <parameter name="AXI_SLICE_SRC" value="0" />
<parameter name="CYCLIC" value="1" /> <parameter name="CYCLIC" value="0" />
<parameter name="DMA_2D_TRANSFER" value="1" /> <parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" /> <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" /> <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" /> <parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="0" /> <parameter name="DMA_TYPE_DEST" value="0" />
<parameter name="DMA_TYPE_SRC" value="2" /> <parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" /> <parameter name="FIFO_SIZE" value="64" />
<parameter name="ID" value="0" /> <parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" /> <parameter name="SYNC_TRANSFER_START" value="0" />
</module> </module>
@ -491,14 +488,14 @@
<parameter name="ASYNC_CLK_SRC_DEST" value="1" /> <parameter name="ASYNC_CLK_SRC_DEST" value="1" />
<parameter name="AXI_SLICE_DEST" value="0" /> <parameter name="AXI_SLICE_DEST" value="0" />
<parameter name="AXI_SLICE_SRC" value="0" /> <parameter name="AXI_SLICE_SRC" value="0" />
<parameter name="CYCLIC" value="1" /> <parameter name="CYCLIC" value="0" />
<parameter name="DMA_2D_TRANSFER" value="1" /> <parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" /> <parameter name="DMA_DATA_WIDTH_DEST" value="256" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" /> <parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" /> <parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="0" /> <parameter name="DMA_TYPE_DEST" value="0" />
<parameter name="DMA_TYPE_SRC" value="2" /> <parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" /> <parameter name="FIFO_SIZE" value="64" />
<parameter name="ID" value="0" /> <parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" /> <parameter name="SYNC_TRANSFER_START" value="0" />
</module> </module>
@ -508,37 +505,37 @@
<parameter name="RX_NUM_OF_LANES" value="4" /> <parameter name="RX_NUM_OF_LANES" value="4" />
<parameter name="TX_NUM_OF_LANES" value="4" /> <parameter name="TX_NUM_OF_LANES" value="4" />
</module> </module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" /> <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" /> <parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" /> <parameter name="USE_RESET_REQUEST" value="0" />
</module> </module>
<module <module
name="rx_ref_clk" name="rx_ref_clk"
kind="altera_clock_bridge" kind="altera_clock_bridge"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="250000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="250000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1"> <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" /> <parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="100000000" /> <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" /> <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module> </module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1"> <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" /> <parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" /> <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" /> <parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" /> <parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" /> <parameter name="USE_RESET_REQUEST" value="0" />
</module> </module>
<module name="util_bsplit" kind="util_bsplit" version="1.0" enabled="1"> <module name="util_bsplit" kind="util_bsplit" version="1.0" enabled="1">
@ -553,7 +550,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="32" /> <parameter name="CHANNEL_DATA_WIDTH" value="32" />
<parameter name="NUM_OF_CHANNELS" value="2" /> <parameter name="NUM_OF_CHANNELS" value="2" />
</module> </module>
<module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1"> <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
<parameter name="ADJCNT" value="0" /> <parameter name="ADJCNT" value="0" />
<parameter name="ADJDIR" value="0" /> <parameter name="ADJDIR" value="0" />
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" /> <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
@ -566,6 +563,13 @@
<parameter name="DID" value="0" /> <parameter name="DID" value="0" />
<parameter name="DLB_TEST" value="0" /> <parameter name="DLB_TEST" value="0" />
<parameter name="ECC_EN" value="0" /> <parameter name="ECC_EN" value="0" />
<parameter name="ED_DEV_KIT" value="NONE" />
<parameter name="ED_FILESET_SIM" value="false" />
<parameter name="ED_FILESET_SYNTH" value="false" />
<parameter name="ED_GENERIC_5SERIES" value="No" />
<parameter name="ED_GENERIC_A10" value="No" />
<parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
<parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
<parameter name="GUI_CFG_F" value="4" /> <parameter name="GUI_CFG_F" value="4" />
<parameter name="GUI_EN_CFG_F" value="false" /> <parameter name="GUI_EN_CFG_F" value="false" />
<parameter name="HD" value="0" /> <parameter name="HD" value="0" />
@ -612,13 +616,13 @@
<module <module
name="xcvr_rst_cntrl" name="xcvr_rst_cntrl"
kind="altera_xcvr_reset_control" kind="altera_xcvr_reset_control"
version="15.0" version="15.1"
enabled="1"> enabled="1">
<parameter name="CHANNELS" value="4" /> <parameter name="CHANNELS" value="4" />
<parameter name="PLLS" value="1" /> <parameter name="PLLS" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" /> <parameter name="REDUCED_SIM_TIME" value="1" />
<parameter name="RX_ENABLE" value="1" /> <parameter name="RX_ENABLE" value="1" />
<parameter name="RX_PER_CHANNEL" value="0" /> <parameter name="RX_PER_CHANNEL" value="1" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" /> <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" /> <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="100" /> <parameter name="SYS_CLK_IN_MHZ" value="100" />
@ -627,8 +631,9 @@
<parameter name="TX_PLL_ENABLE" value="0" /> <parameter name="TX_PLL_ENABLE" value="0" />
<parameter name="T_PLL_LOCK_HYST" value="0" /> <parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" /> <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" /> <parameter name="T_RX_ANALOGRESET" value="80" />
<parameter name="T_RX_DIGITALRESET" value="4000" /> <parameter name="T_RX_DIGITALRESET" value="8000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" /> <parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria V" /> <parameter name="device_family" value="Arria V" />
<parameter name="gui_pll_cal_busy" value="0" /> <parameter name="gui_pll_cal_busy" value="0" />
@ -636,7 +641,7 @@
<parameter name="gui_split_interfaces" value="0" /> <parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="1" /> <parameter name="gui_tx_auto_reset" value="1" />
</module> </module>
<module name="xcvr_rx_pll" kind="altera_pll" version="15.0" enabled="1"> <module name="xcvr_rx_pll" kind="altera_pll" version="15.1" enabled="1">
<parameter name="debug_print_output" value="false" /> <parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" /> <parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5AGTFD7K3F40I3" /> <parameter name="device" value="5AGTFD7K3F40I3" />
@ -699,7 +704,7 @@
<parameter name="gui_cascade_outclk_index" value="0" /> <parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" /> <parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" /> <parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="1" /> <parameter name="gui_device_speed_grade" value="2" />
<parameter name="gui_divide_factor_c0" value="1" /> <parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" /> <parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" /> <parameter name="gui_divide_factor_c10" value="1" />
@ -841,114 +846,112 @@
</module> </module>
<connection <connection
kind="avalon_streaming" kind="avalon_streaming"
version="15.0" version="15.1"
start="xcvr_core.jesd204_rx_link" start="xcvr_core.jesd204_rx_link"
end="axi_jesd_xcvr.if_rx_ip_avl" /> end="axi_jesd_xcvr.if_rx_ip_avl" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9250_0.if_adc_clk" start="axi_ad9250_0.if_adc_clk"
end="util_cpack_0.if_adc_clk" /> end="util_cpack_0.if_adc_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9250_1.if_adc_clk" start="axi_ad9250_1.if_adc_clk"
end="util_cpack_1.if_adc_clk" /> end="util_cpack_1.if_adc_clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="axi_ad9250_1.if_adc_clk"
end="axi_dmac_1.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.1"
start="axi_ad9250_0.if_adc_clk"
end="axi_dmac_0.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="xcvr_rst_cntrl.clock" /> end="xcvr_rst_cntrl.clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="xcvr_core.jesd204_rx_avs_clk" /> end="xcvr_core.jesd204_rx_avs_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_dmac_1.m_dest_axi_clock" /> end="axi_dmac_1.m_dest_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="mem_clk.out_clk" start="mem_clk.out_clk"
end="axi_dmac_0.m_dest_axi_clock" /> end="axi_dmac_0.m_dest_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="rx_ref_clk.out_clk" start="rx_ref_clk.out_clk"
end="xcvr_core.pll_ref_clk" /> end="xcvr_core.pll_ref_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="rx_ref_clk.out_clk" start="rx_ref_clk.out_clk"
end="xcvr_rx_pll.refclk" /> end="xcvr_rx_pll.refclk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9250_1.s_axi_clock" /> end="axi_ad9250_1.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_dmac_0.s_axi_clock" /> end="axi_dmac_0.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_dmac_1.s_axi_clock" /> end="axi_dmac_1.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_jesd_xcvr.s_axi_clock" /> end="axi_jesd_xcvr.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="sys_clk.out_clk" start="sys_clk.out_clk"
end="axi_ad9250_0.s_axi_clock" /> end="axi_ad9250_0.s_axi_clock" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_dmac_1.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.0"
start="xcvr_rx_pll.outclk0"
end="axi_dmac_0.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.0"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_ad9250_1.if_rx_clk" /> end="axi_ad9250_1.if_rx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_ad9250_0.if_rx_clk" /> end="axi_ad9250_0.if_rx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_rx_clk" /> end="axi_jesd_xcvr.if_rx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_tx_clk" /> end="axi_jesd_xcvr.if_tx_clk" />
<connection <connection
kind="clock" kind="clock"
version="15.0" version="15.1"
start="xcvr_rx_pll.outclk0" start="xcvr_rx_pll.outclk0"
end="xcvr_core.rxlink_clk" /> end="xcvr_core.rxlink_clk" />
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.dev_lane_aligned" start="xcvr_core.dev_lane_aligned"
end="xcvr_core.alldev_lane_aligned"> end="xcvr_core.alldev_lane_aligned">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -959,7 +962,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9250_0.fifo_ch_0_in" start="axi_ad9250_0.fifo_ch_0_in"
end="util_cpack_0.fifo_ch_0"> end="util_cpack_0.fifo_ch_0">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -970,7 +973,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9250_1.fifo_ch_0_in" start="axi_ad9250_1.fifo_ch_0_in"
end="util_cpack_1.fifo_ch_0"> end="util_cpack_1.fifo_ch_0">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -981,7 +984,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9250_0.fifo_ch_1_in" start="axi_ad9250_0.fifo_ch_1_in"
end="util_cpack_0.fifo_ch_1"> end="util_cpack_0.fifo_ch_1">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -992,7 +995,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9250_1.fifo_ch_1_in" start="axi_ad9250_1.fifo_ch_1_in"
end="util_cpack_1.fifo_ch_1"> end="util_cpack_1.fifo_ch_1">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1003,7 +1006,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_0.if_adc_data" start="util_cpack_0.if_adc_data"
end="axi_dmac_0.if_fifo_wr_din"> end="axi_dmac_0.if_fifo_wr_din">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1014,7 +1017,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_1.if_adc_data" start="util_cpack_1.if_adc_data"
end="axi_dmac_1.if_fifo_wr_din"> end="axi_dmac_1.if_fifo_wr_din">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1025,7 +1028,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_0.if_adc_sync" start="util_cpack_0.if_adc_sync"
end="axi_dmac_0.if_fifo_wr_sync"> end="axi_dmac_0.if_fifo_wr_sync">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1036,7 +1039,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_cpack_1.if_adc_sync" start="util_cpack_1.if_adc_sync"
end="axi_dmac_1.if_fifo_wr_sync"> end="axi_dmac_1.if_fifo_wr_sync">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1047,7 +1050,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_0.if_fifo_wr_en" start="axi_dmac_0.if_fifo_wr_en"
end="util_cpack_0.if_adc_valid"> end="util_cpack_0.if_adc_valid">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1058,7 +1061,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_1.if_fifo_wr_en" start="axi_dmac_1.if_fifo_wr_en"
end="util_cpack_1.if_adc_valid"> end="util_cpack_1.if_adc_valid">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1069,7 +1072,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_0.if_fifo_wr_overflow" start="axi_dmac_0.if_fifo_wr_overflow"
end="axi_ad9250_0.if_adc_dovf"> end="axi_ad9250_0.if_adc_dovf">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1080,7 +1083,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_dmac_1.if_fifo_wr_overflow" start="axi_dmac_1.if_fifo_wr_overflow"
end="axi_ad9250_1.if_adc_dovf"> end="axi_ad9250_1.if_adc_dovf">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1091,7 +1094,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_data" start="axi_jesd_xcvr.if_rx_data"
end="util_bsplit.if_data"> end="util_bsplit.if_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1102,7 +1105,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_ad9250_0.if_rx_data" start="axi_ad9250_0.if_rx_data"
end="util_bsplit.if_split_data_0"> end="util_bsplit.if_split_data_0">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1113,7 +1116,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sync" start="axi_jesd_xcvr.if_rx_ip_sync"
end="xcvr_core.dev_sync_n"> end="xcvr_core.dev_sync_n">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1124,7 +1127,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sysref" start="axi_jesd_xcvr.if_rx_ip_sysref"
end="xcvr_core.sysref"> end="xcvr_core.sysref">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1135,7 +1138,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="util_bsplit.if_split_data_1" start="util_bsplit.if_split_data_1"
end="axi_ad9250_1.if_rx_data"> end="axi_ad9250_1.if_rx_data">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1146,7 +1149,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.rx_analogreset" start="xcvr_rst_cntrl.rx_analogreset"
end="xcvr_core.rx_analogreset"> end="xcvr_core.rx_analogreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1157,7 +1160,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.rx_cal_busy" start="xcvr_core.rx_cal_busy"
end="xcvr_rst_cntrl.rx_cal_busy"> end="xcvr_rst_cntrl.rx_cal_busy">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1168,7 +1171,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.rx_digitalreset" start="xcvr_core.rx_digitalreset"
end="xcvr_rst_cntrl.rx_digitalreset"> end="xcvr_rst_cntrl.rx_digitalreset">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1179,7 +1182,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.rx_is_lockedtodata" start="xcvr_rst_cntrl.rx_is_lockedtodata"
end="xcvr_core.rx_islockedtodata"> end="xcvr_core.rx_islockedtodata">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1190,7 +1193,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_rst_cntrl.rx_ready" start="xcvr_rst_cntrl.rx_ready"
end="axi_jesd_xcvr.if_rx_ready"> end="axi_jesd_xcvr.if_rx_ready">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1201,7 +1204,7 @@
</connection> </connection>
<connection <connection
kind="conduit" kind="conduit"
version="15.0" version="15.1"
start="xcvr_core.sof" start="xcvr_core.sof"
end="axi_jesd_xcvr.if_rx_ip_sof"> end="axi_jesd_xcvr.if_rx_ip_sof">
<parameter name="endPort" value="" /> <parameter name="endPort" value="" />
@ -1212,72 +1215,67 @@
</connection> </connection>
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_ad9250_1.if_adc_rst" start="axi_ad9250_1.if_adc_rst"
end="util_cpack_1.if_adc_rst" /> end="util_cpack_1.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_ad9250_0.if_adc_rst" start="axi_ad9250_0.if_adc_rst"
end="util_cpack_0.if_adc_rst" /> end="util_cpack_0.if_adc_rst" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.0"
start="axi_jesd_xcvr.if_rst" start="axi_jesd_xcvr.if_rst"
end="xcvr_rx_pll.reset" /> end="xcvr_rx_pll.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="axi_jesd_xcvr.if_rx_rstn" start="axi_jesd_xcvr.if_rx_rstn"
end="xcvr_core.rxlink_rst_n" /> end="xcvr_core.rxlink_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_core.jesd204_rx_avs_rst_n" /> end="xcvr_core.jesd204_rx_avs_rst_n" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_dmac_1.m_dest_axi_reset" /> end="axi_dmac_1.m_dest_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="mem_rst.out_reset" start="mem_rst.out_reset"
end="axi_dmac_0.m_dest_axi_reset" /> end="axi_dmac_0.m_dest_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" /> end="xcvr_rst_cntrl.reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9250_1.s_axi_reset" /> end="axi_ad9250_1.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_dmac_0.s_axi_reset" /> end="axi_dmac_0.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_dmac_1.s_axi_reset" /> end="axi_dmac_1.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_jesd_xcvr.s_axi_reset" /> end="axi_jesd_xcvr.s_axi_reset" />
<connection <connection
kind="reset" kind="reset"
version="15.0" version="15.1"
start="sys_rst.out_reset" start="sys_rst.out_reset"
end="axi_ad9250_0.s_axi_reset" /> end="axi_ad9250_0.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

5
projects/fmcjesdadc1/kc705/system_bd.tcl
View File

@ -2,3 +2,8 @@
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source ../common/fmcjesdadc1_bd.tcl source ../common/fmcjesdadc1_bd.tcl
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {512}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.FIFO_SIZE {32}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {512}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.FIFO_SIZE {32}] $axi_ad9250_1_dma

2
projects/fmcjesdadc1/kc705/system_constr.xdc
View File

@ -21,4 +21,4 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks # clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

4
projects/fmcjesdadc1/vc707/system_bd.tcl
View File

@ -2,3 +2,7 @@
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/fmcjesdadc1_bd.tcl source ../common/fmcjesdadc1_bd.tcl
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.FIFO_SIZE {32}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.FIFO_SIZE {32}] $axi_ad9250_1_dma

1
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -21,3 +21,4 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio
# clocks # clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -21,3 +21,4 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks # clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

3
projects/fmcomms5/common/fmcomms5_bd.tcl
View File

@ -108,7 +108,8 @@ ad_connect axi_ad9361_0_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect sys_cpu_resetn sys_100m_resetn ad_connect sys_cpu_resetn sys_100m_resetn
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
ad_connect sys_cpu_resetn util_cpack_adc/adc_rst ad_connect sys_cpu_reset util_cpack_adc/adc_rst
ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out
ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in

4
projects/fmcomms6/common/fmcomms6_bd.tcl
View File

@ -44,8 +44,8 @@ ad_connect axi_ad9652/adc_rst axi_ad9652_adc_fifo/din_rst
ad_connect sys_200m_clk axi_ad9652/delay_clk ad_connect sys_200m_clk axi_ad9652/delay_clk
ad_connect sys_200m_clk axi_ad9652_dma/fifo_wr_clk ad_connect sys_200m_clk axi_ad9652_dma/fifo_wr_clk
ad_connect sys_200m_clk data_pack/adc_clk ad_connect sys_200m_clk data_pack/adc_clk
ad_connect sys_cpu_resetn data_pack/adc_rst ad_connect sys_cpu_reset data_pack/adc_rst
ad_connect axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0 ad_connect axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0
ad_connect axi_ad9652/adc_valid_0 axi_ad9652_adc_fifo/din_valid_0 ad_connect axi_ad9652/adc_valid_0 axi_ad9652_adc_fifo/din_valid_0

4
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
View File

@ -206,7 +206,7 @@
ad_connect sys_cpu_clk current_monitor_m1_pack/adc_clk ad_connect sys_cpu_clk current_monitor_m1_pack/adc_clk
ad_connect sys_cpu_resetn current_monitor_m1_pack/adc_rst ad_connect sys_cpu_reset current_monitor_m1_pack/adc_rst
ad_connect current_monitor_m1/adc_enable_ia current_monitor_m1_pack/adc_enable_0 ad_connect current_monitor_m1/adc_enable_ia current_monitor_m1_pack/adc_enable_0
ad_connect current_monitor_m1/adc_enable_ib current_monitor_m1_pack/adc_enable_1 ad_connect current_monitor_m1/adc_enable_ib current_monitor_m1_pack/adc_enable_1
@ -231,7 +231,7 @@
ad_connect adc_m2_vbus_dat_i current_monitor_m2/adc_vbus_dat_i ad_connect adc_m2_vbus_dat_i current_monitor_m2/adc_vbus_dat_i
ad_connect sys_cpu_clk current_monitor_m2_pack/adc_clk ad_connect sys_cpu_clk current_monitor_m2_pack/adc_clk
ad_connect sys_cpu_resetn current_monitor_m2_pack/adc_rst ad_connect sys_cpu_reset current_monitor_m2_pack/adc_rst
ad_connect current_monitor_m2/adc_enable_ia current_monitor_m2_pack/adc_enable_0 ad_connect current_monitor_m2/adc_enable_ia current_monitor_m2_pack/adc_enable_0
ad_connect current_monitor_m2/adc_enable_ib current_monitor_m2_pack/adc_enable_1 ad_connect current_monitor_m2/adc_enable_ib current_monitor_m2_pack/adc_enable_1