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data_offload: Improve timing in regmap

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Istvan Csomortani 2021-03-19 08:11:42 +00:00 committed by Mihaita Nagy
parent c27a0e4add
commit 378daf031c
1 changed files with 4 additions and 2 deletions
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6
library/data_offload/data_offload_regmap.v
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@ -77,7 +77,7 @@ module data_offload_regmap #(
output sync,
output [ 1:0] sync_config,
output [31:0] src_transfer_length,
output reg [31:0] src_transfer_length,
// FSM control and status
input [ 1:0] src_fsm_status,
@ -112,6 +112,7 @@ module data_offload_regmap #(
wire [31:0] up_sample_count_lsb_s;
wire src_sw_resetn_s;
wire dst_sw_resetn_s;
wire [31:0] src_transfer_length_s;
// write interface
always @(posedge up_clk) begin
@ -361,11 +362,12 @@ module data_offload_regmap #(
.in_clk (up_clk),
.in_data (up_transfer_length),
.out_clk (src_clk),
.out_data (src_transfer_length)
.out_data (src_transfer_length_s)
);
always @(posedge src_clk) begin
src_sw_resetn <= src_sw_resetn_s;
src_transfer_length <= src_transfer_length_s;
end
always @(posedge dst_clk) begin