From 37a1c98c12bf4232857e726d70eff527f61eb5e6 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 27 Feb 2017 14:19:54 +0200 Subject: [PATCH] axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching --- library/axi_logic_analyzer/axi_logic_analyzer.v | 2 +- library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v index e00a7920c..1e3b15827 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -142,7 +142,7 @@ module axi_logic_analyzer ( end endgenerate - BUFGMUX BUFGMUX_inst ( + BUFGMUX_CTRL BUFGMUX_CTRL_inst ( .O (clk_out), .I0 (data_i[0]), .I1 (trigger_i[0]), diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc index b76aee814..f7bb17952 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc +++ b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc @@ -28,3 +28,4 @@ set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]