adi_board.tcl : General update
- Split the adi_dma_interconnect to two procedure: adi_dma_interconnect and adi_hp_assign - Fix the adi_spi_core - Fix the adi_interconnect_litemain
Istvan Csomortani
parent
96541f0a7f
commit
37e2059fd0
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@ -3,167 +3,173 @@
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#----------------------------------------------------------------------------
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# ensure that in case of a port number less than 10, the number format to be 0X
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proc set_num {number} {
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# usage: get_numstr 2
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proc get_numstr {number} {
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if { $number < 10} {
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return "0${number}"
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} else {
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return $number
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}
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}
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# search the first free HP port in case of a Zynq device
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proc free_hp_port { sys_ps7 } {
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set hp_port_num 0
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set hp_port 1
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while { $hp_port == 1 } {
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set hp_port_num [expr $hp_port_num + 1]
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set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" $sys_ps7]
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}
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return $hp_port_num
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}
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#----------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# Integration processes
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#----------------------------------------------------------------------------
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# For AXI_LITE interconnect connections
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proc adi_interconnect_lite { peripheral_name peripheral_address } {
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#------------------------------------------------------------------------------
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# usage : adi_interconnect_lite axi_ad9467
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#------------------------------------------------------------------------------
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proc adi_interconnect_lite { p_name } {
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set peripheral_port_name "s_axi"
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set peripheral_base_name "axi_lite"
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set peripheral_address_range 0x00010000
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set interconnect_bd [get_bd_cells axi_cpu_interconnect]
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set axi_cpu_interconnect [get_bd_cells axi_cpu_interconnect]
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# increment the number of the master ports of the interconnect
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set number_of_master [get_property CONFIG.NUM_MI $interconnect_bd]
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set number_of_master [expr $number_of_master + 1]
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set_property CONFIG.NUM_MI $number_of_master $interconnect_bd
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set p_port [get_property CONFIG.NUM_MI $axi_cpu_interconnect]
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set i_count [expr $p_port + 1]
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set i_str [get_numstr $p_port]
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_seg_fields [split $p_seg "/"]
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lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
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set_property CONFIG.NUM_MI $i_count [get_bd_cells axi_cpu_interconnect]
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
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[get_bd_pins "$axi_cpu_interconnect/M${i_str}_ACLK"] \
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[get_bd_pins "${p_name}/s_axi_aclk"] \
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$::sys_100m_clk_source
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# connect clk and reset for the peripheral port
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${peripheral_name}/s_axi_aclk"]
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
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} else {
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
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[get_bd_pins "${axi_cpu_interconnect}/M${i_str}_ARESETN"] \
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[get_bd_pins "${p_name}/s_axi_aresetn"] \
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$::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${peripheral_name}/s_axi_aclk"]
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
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}
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# make the interface connection
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connect_bd_intf_net -intf_net "${p_name}axi_lite" \
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[get_bd_intf_pins "${axi_cpu_interconnect}/M${i_str}_AXI"] \
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[get_bd_intf_pins "${p_seg_name}/${p_seg_intf}"]
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# if peripheral is a Xilinx core
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if { [regexp "^analog*" [get_property VLNV [get_bd_cells $peripheral_name]]] == 0 } {
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set peripheral_base_name "Reg"
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if { [regexp "^xilinx.*spi*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
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set peripheral_port_name "axi_lite"
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} elseif { [regexp "^xilinx.*dma*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
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set peripheral_port_name "S_AXI_LITE"
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} else {
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set peripheral_port_name "s_axi"
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}
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}
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# make the port connection
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connect_bd_intf_net -intf_net "axi_cpu_interconnect_m${number_of_master}" \
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[get_bd_intf_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_AXI"] \
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[get_bd_intf_pins "${peripheral_name}/${peripheral_port_name}"]
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# define address space for the peripheral
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create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address \
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$::sys_addr_cntrl_space \
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[get_bd_addr_segs "${peripheral_name}/${peripheral_port_name}/${peripheral_base_name}"] \
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"SEG_data_${peripheral_name}_axi_lite"
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}
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# Set up the SPI core
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proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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#------------------------------------------------------------------------------
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# usage: adi_assign_base_address 0x74a00000 axi_ad9467
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#------------------------------------------------------------------------------
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proc adi_assign_base_address {p_addr p_name} {
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_seg_fields [split $p_seg "/"]
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lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
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set p_seg_range [get_property range $p_seg]
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create_bd_addr_seg -range $p_seg_range \
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-offset $p_addr $::sys_addr_cntrl_space \
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$p_seg "SEG_data_${p_name}"
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}
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#------------------------------------------------------------------------------
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# usage : adi_add_interrupt axi_ad9467_dma/irq
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#------------------------------------------------------------------------------
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proc adi_add_interrupt { intr_port } {
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if { [get_bd_ports unc_int2] != {} } {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2]
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connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins $intr_port]
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} elseif { [get_bd_ports unc_int3] != {} } {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3]
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connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins $intr_port]
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} else {
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set p_intr [get_property CONFIG.NUM_PORTS [get_bd_cells sys_concat_intc]]
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set i_intr [expr $p_intr + 1]
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set_property CONFIG.NUM_PORTS $i_intr [get_bd_cells sys_concat_intc]
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connect_bd_net -net "sys_concat_intc_din_${i_intr}" \
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[get_bd_pins "sys_concat_intc/In${i_intr}"] \
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[get_bd_pins $intr_port]
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}
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# incrase the auxiliary concat last input port
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if { $::sys_zynq == 0 } {
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set p_aux_intr [get_property CONFIG.IN9_WIDTH [get_bd_cells sys_concat_aux_intc]]
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set i_aux_intc [expr $p_aux_intr + 1]
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set_property CONFIG.IN9_WIDTH $i_aux_intr [get_bd_cells sys_concat_aux_intc]
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}
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}
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#------------------------------------------------------------------------------
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# usage : adi_spi_core 0x41600000 2 ad9467_spi
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#------------------------------------------------------------------------------
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proc adi_spi_core { spi_addr spi_ss spi_name } {
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# define SPI ports
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set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
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set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
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set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
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set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
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set spi_miso_i [create_bd_port -dir I spi_miso_i]
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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create_bd_port -dir I ${spi_name}_sclk_i
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create_bd_port -dir O ${spi_name}_sclk_o
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create_bd_port -dir I ${spi_name}_mosi_i
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create_bd_port -dir O ${spi_name}_mosi_o
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create_bd_port -dir I ${spi_name}_miso_i
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create_bd_port -dir I ${spi_name}_csn_i
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create_bd_port -dir O -from [expr $spi_ss - 1] -to 0 ${spi_name}_csn_o
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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set sys_ps7 [get_bd_cells sys_ps7]
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# add SPI interface to ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells sys_ps7]
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] [get_bd_cells sys_ps7]
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# add SPI interface to ps7, first check which SPI is free
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if { [get_property CONFIG.PCW_SPI0_PERIPHERAL_ENABLE [get_bd_cells sys_ps7]] == 0 } {
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set if_spi "SPI0"
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} else {
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI0_IO {EMIO}] $sys_ps7
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set if_spi "SPI1"
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}
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# connect chipselect lines to the ports
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if { $spi_ss > 1 } {
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create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 ${spi_name}_csn_concat
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set_property CONFIG.NUM_PORTS $spi_ss [get_bd_cells ${spi_name}_csn_concat]
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connect_bd_net -net ${spi_name}_csn_o \
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[get_bd_ports ${spi_name}_csn_o] \
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[get_bd_pins ${spi_name}_csn_concat/dout]
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set i 0
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while { $i < $spi_ss_width } {
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if { $i == 0 } {
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set ps7_cs "sys_ps7/SPI0_SS_O"
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set j [expr $spi_ss - 1]
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while { $i < $spi_ss } {
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if { $j == 0 } {
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set ss_number SS
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} else {
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set ps7_cs "sys_ps7/SPI0_SS${i}_O"
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}
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switch $i {
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0
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{ set spi_csn0_o [create_bd_port -dir O spi_csn0_o]
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connect_bd_net -net "spi_csn${i}" \
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[get_bd_pins $ps7_cs] \
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[get_bd_ports spi_csn0_o]
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}
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1
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{ set spi_csn1_o [create_bd_port -dir O spi_csn1_o]
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connect_bd_net -net "spi_csn${i}" \
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[get_bd_pins $ps7_cs] \
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[get_bd_ports spi_csn1_o]
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}
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2
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{ set spi_csn2_o [create_bd_port -dir O spi_csn2_o]
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connect_bd_net -net "spi_csn${i}" \
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[get_bd_pins $ps7_cs] \
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[get_bd_ports spi_csn2_o]
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}
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3
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{ set spi_csn3_o [create_bd_port -dir O spi_csn3_o]
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connect_bd_net -net "spi_csn${i}" \
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[get_bd_pins $ps7_cs] \
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[get_bd_ports spi_csn3_o]
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}
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set ss_number SS${j}
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}
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connect_bd_net [get_bd_pins ${spi_name}_csn_concat/In${i}] \
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[get_bd_pins sys_ps7/${if_spi}_${ss_number}_O]
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incr i
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incr j -1
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}
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} else {
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connect_bd_net -net ${spi_name}_csn_o \
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[get_bd_ports ${spi_name}_csn_o] \
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[get_bd_pins sys_ps7/${if_spi}_SS_O]
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}
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# connect remaining nets to the ports
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connect_bd_net -net spi_csn_i \
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[get_bd_ports spi_csn_i] \
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[get_bd_pins sys_ps7/SPI0_SS_I]
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[get_bd_pins sys_ps7/${if_spi}_SS_I]
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connect_bd_net -net spi_sclk_i \
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[get_bd_ports spi_sclk_i] \
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[get_bd_pins sys_ps7/SPI0_SCLK_I]
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[get_bd_pins sys_ps7/${if_spi}_SCLK_I]
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connect_bd_net -net spi_sclk_o \
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[get_bd_ports spi_sclk_o] \
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[get_bd_pins sys_ps7/SPI0_SCLK_O]
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[get_bd_pins sys_ps7/${if_spi}_SCLK_O]
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connect_bd_net -net spi_mosi_i \
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[get_bd_ports spi_mosi_i] \
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[get_bd_pins sys_ps7/SPI0_MOSI_I]
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[get_bd_pins sys_ps7/${if_spi}_MOSI_I]
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connect_bd_net -net spi_mosi_o \
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[get_bd_ports spi_mosi_o] \
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[get_bd_pins sys_ps7/SPI0_MOSI_O]
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[get_bd_pins sys_ps7/${if_spi}_MOSI_O]
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connect_bd_net -net spi_miso_i \
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[get_bd_ports spi_miso_i] \
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[get_bd_pins sys_ps7/SPI0_MISO_I]
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[get_bd_pins sys_ps7/${if_spi}_MISO_I]
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} else {
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# SPI SS lines
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set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
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# instanciate AXI_SPI core
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set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
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@ -171,26 +177,8 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
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set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
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switch $spi_ss_width {
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1
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $spi_name
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}
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2
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $spi_name
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}
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3
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $spi_name
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}
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4
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{
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set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $spi_name
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}
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}
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set_property CONFIG.C_NUM_SS_BITS $spi_ss $spi_name
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adi_interconnect_lite $spi_name $spi_base_addr
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${spi_name}/ext_spi_clk"] \
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$::sys_100m_clk_source
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@ -220,103 +208,74 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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}
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}
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# For AXI interconnect connections between dma and 'ddr controller'/HP port
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proc adi_dma_interconnect { dma_name port_name} {
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#------------------------------------------------------------------------------
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# adi_dma_interconnect axi_ad9467_dma/m_dest_axi sys_200m_clk axi_mem_interconnect
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#------------------------------------------------------------------------------
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proc adi_dma_interconnect { dma_if dma_clk ic_name } {
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# check processor type, connect system clock and reset to the peripheral
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if { $::sys_zynq == 1 } {
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set dma_atrb [split $dma_if "/"]
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lassign $dma_atrb dma_name dma_if_port
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set hp_port [free_hp_port [get_bd_cells sys_ps7]]
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set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
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switch $hp_port {
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1
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{
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set axi_dma_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_1]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_1
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}
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2
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{
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set axi_dma_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_2]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_2
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}
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3
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{
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set axi_dma_interconnect_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_3]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_3
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}
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}
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# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk \
|
||||
[get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn \
|
||||
[get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
|
||||
connect_bd_intf_net -intf_net axi_dma_interconnect_m00_axi \
|
||||
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \
|
||||
[get_bd_intf_pins sys_ps7/S_AXI_HP1]
|
||||
|
||||
# connect clk and reset for the interconnect
|
||||
connect_bd_net -net sys_100m_clk \
|
||||
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ACLK"] \
|
||||
$::sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn \
|
||||
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ARESETN"] \
|
||||
$::sys_100m_resetn_source
|
||||
|
||||
# connect clk and reset for the peripheral port
|
||||
puts "${dma_name}/${port_name}_aclk"
|
||||
connect_bd_net -net sys_100m_clk \
|
||||
[get_bd_pins "${dma_name}/${port_name}_aclk"]
|
||||
connect_bd_net -net sys_100m_resetn \
|
||||
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
|
||||
|
||||
# Connect the interconnect to the dma
|
||||
connect_bd_intf_net -intf_net "axi_dma_interconnect_${hp_port}_s00_axi" \
|
||||
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \
|
||||
[get_bd_intf_pins "${dma_name}/${port_name}"]
|
||||
|
||||
# Definte address space
|
||||
create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
|
||||
[get_bd_addr_spaces "${dma_name}/${port_name}"] \
|
||||
[get_bd_addr_segs "sys_ps7/S_AXI_HP${hp_port}/HP${hp_port}_DDR_LOWOCM"] \
|
||||
"SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
|
||||
# increment the number of the slave ports of the interconnect
|
||||
set p_port [get_property CONFIG.NUM_SI [get_bd_cells $ic_name]]
|
||||
if { $p_port == 1} {
|
||||
if { [get_bd_intf_nets -of_object [get_bd_intf_pins "${ic_name}/S00_AXI"]] eq {} } {
|
||||
set i_count 1
|
||||
set i_str [get_numstr 0]
|
||||
} else {
|
||||
set i_count [expr $p_port + 1]
|
||||
set i_str [get_numstr $p_port]
|
||||
}
|
||||
} else {
|
||||
set i_count [expr $p_port + 1]
|
||||
set i_str [get_numstr $p_port]
|
||||
}
|
||||
|
||||
set axi_mem_interconnect [get_bd_cells axi_mem_interconnect]
|
||||
|
||||
# increment the number of the master ports of the interconnect
|
||||
set number_of_slave [get_property CONFIG.NUM_SI $axi_mem_interconnect]
|
||||
set number_of_slave [expr $number_of_slave + 1]
|
||||
set_property CONFIG.NUM_SI $number_of_slave $axi_mem_interconnect
|
||||
set_property CONFIG.NUM_SI $i_count [get_bd_cells $ic_name]
|
||||
|
||||
# connect clk and reset for the interconnect
|
||||
connect_bd_net -net sys_100m_clk \
|
||||
[get_bd_pins "${axi_mem_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
|
||||
$::sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn \
|
||||
[get_bd_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
|
||||
connect_bd_net [get_bd_pins "${ic_name}/S${i_str}_ACLK"] \
|
||||
${dma_clk}
|
||||
connect_bd_net -net "${dma_name}_ic_resetn" \
|
||||
[get_bd_pins "${ic_name}/S${i_str}_ARESETN"] \
|
||||
$::sys_100m_resetn_source
|
||||
|
||||
# connect clk and reset for the peripheral port
|
||||
connect_bd_net -net sys_100m_clk \
|
||||
[get_bd_pins "${dma_name}/${port_name}_aclk"]
|
||||
connect_bd_net -net "${dma_name}_aclk" \
|
||||
[get_bd_pins "${dma_name}/${dma_if_port}_aclk"]
|
||||
connect_bd_net -net sys_100m_resetn \
|
||||
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
|
||||
[get_bd_pins "${dma_name}/${dma_if_port}_aresetn"]
|
||||
|
||||
# make the port connection
|
||||
connect_bd_intf_net -intf_net "axi_mem_interconnect_s${number_of_slave}" \
|
||||
[get_bd_intf_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_AXI"] \
|
||||
[get_bd_intf_pins "${dma_name}/${port_name}"]
|
||||
connect_bd_intf_net -intf_net "${dma_name}_${i_str}" \
|
||||
[get_bd_intf_pins "${ic_name}/S${i_str}_AXI"] \
|
||||
[get_bd_intf_pins "${dma_name}/${dma_if_port}"]
|
||||
|
||||
# define address space for the peripheral
|
||||
create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
|
||||
[get_bd_addr_spaces "${dma_name}/${port_name}"] \
|
||||
[get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \
|
||||
"SEG_data_${dma_name}_2_ddr"
|
||||
}
|
||||
assign_bd_address
|
||||
}
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# usage : adi_hp_assign 1
|
||||
#------------------------------------------------------------------------------
|
||||
proc adi_hp_assign { hp_port } {
|
||||
|
||||
# check is hp port is enabled
|
||||
if { [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port}" [get_bd_cells sys_ps7]] == 1 } {
|
||||
#return the interconnect of the hp port
|
||||
set hp_net [get_bd_intf_nets -of_objects [get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]]
|
||||
set hp_net_cells [get_bd_cells -of_obkects $hp_net]
|
||||
set idx [lsearch $hp_net_cells "/sys_ps7"]
|
||||
set ic_hp [lreplace $hp_net_cells $idx $idx]
|
||||
} else {
|
||||
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp${hp_port}_interconnect
|
||||
connect_bd_intf_net -intf_net "axi_hp${hp_port}_interconnect_m00_axi" \
|
||||
[get_bd_intf_pins "axi_hp${hp_port}_interconnect/M00_AXI"] \
|
||||
[get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]
|
||||
set ic_hp "axi_hp${hp_port}_interconnect"
|
||||
}
|
||||
|
||||
return $ic_hp
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue