usdrx1: spi signal definitions
parent
06b28d2e24
commit
38126c404c
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@ -204,16 +204,12 @@ module system_top (
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// internal signals
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wire [10:0] spi_csn;
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wire [43:0] gpio_i;
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wire [43:0] gpio_o;
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wire [43:0] gpio_t;
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wire afe_mlo;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire [ 1:0] gpio_open;
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wire [511:0] adc_ddata;
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wire [127:0] adc_ddata_0;
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wire [127:0] adc_ddata_1;
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@ -239,6 +235,10 @@ module system_top (
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wire [63:0] gt_rx_data_1;
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wire [63:0] gt_rx_data_2;
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wire [63:0] gt_rx_data_3;
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wire [43:0] gpio_i;
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wire [43:0] gpio_o;
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wire [43:0] gpio_t;
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wire afe_mlo;
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// spi assignments
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@ -275,13 +275,12 @@ module system_top (
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assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0;
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assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0;
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assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0};
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assign adc_dovf_0 = adc_dovf;
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assign adc_dovf_1 = adc_dovf;
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assign adc_dovf_2 = adc_dovf;
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assign adc_dovf_3 = adc_dovf;
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// instantiations
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// data interface
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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@ -300,6 +299,8 @@ module system_top (
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.O (rx_sync_p),
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.OB (rx_sync_n));
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// gpio/control interface
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OBUFDS i_obufds_mlo (
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.I (afe_mlo),
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.O (afe_mlo_p),
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