From 386cc74ab4f4b5ca3b4b1b9ba98bf0fecf19c037 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 25 Aug 2015 09:41:34 +0300 Subject: [PATCH] util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl Fix port names at the 'port_maps' attribute of the adi_add_bus process call. --- library/util_axis_fifo/util_axis_fifo_ip.tcl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/library/util_axis_fifo/util_axis_fifo_ip.tcl b/library/util_axis_fifo/util_axis_fifo_ip.tcl index 61f212c2a..014409288 100644 --- a/library/util_axis_fifo/util_axis_fifo_ip.tcl +++ b/library/util_axis_fifo/util_axis_fifo_ip.tcl @@ -18,18 +18,18 @@ adi_add_bus "S_AXIS" "slave" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ { - {"s_valid" "TVALID"} \ - {"s_ready" "TREADY"} \ - {"s_data" "TDATA"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ } adi_add_bus "M_AXIS" "master" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ { - {"m_valid" "TVALID"} \ - {"m_ready" "TREADY"} \ - {"m_data" "TDATA"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ } adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn"