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util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl 

Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
main
Istvan Csomortani 2015-08-25 09:41:34 +03:00
parent c2ea667a01
commit 386cc74ab4
1 changed files with 6 additions and 6 deletions
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12
library/util_axis_fifo/util_axis_fifo_ip.tcl
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@ -18,18 +18,18 @@ adi_add_bus "S_AXIS" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ {
{"s_valid" "TVALID"} \ {"s_axis_valid" "TVALID"} \
{"s_ready" "TREADY"} \ {"s_axis_ready" "TREADY"} \
{"s_data" "TDATA"} \ {"s_axis_data" "TDATA"} \
} }
adi_add_bus "M_AXIS" "master" \ adi_add_bus "M_AXIS" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ {
{"m_valid" "TVALID"} \ {"m_axis_valid" "TVALID"} \
{"m_ready" "TREADY"} \ {"m_axis_ready" "TREADY"} \
{"m_data" "TDATA"} \ {"m_axis_data" "TDATA"} \
} }
adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn" adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn"