From 38f495b2cf4c910672c150f45c0deb4fd5c0a473 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Aug 2017 14:40:24 +0200 Subject: [PATCH] axi_i2s_adi: Make constraints work on UltraScale The 'PRIMITIVE_SUBGROUP == flop' filter only works on 7-Series. Replace it with 'IS_SEQUENTIAL' which works on both 7-Series and UltraScale. Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi_constr.xdc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi_constr.xdc b/library/axi_i2s_adi/axi_i2s_adi_constr.xdc index f3ea44e28..8894a53b1 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_constr.xdc +++ b/library/axi_i2s_adi/axi_i2s_adi_constr.xdc @@ -6,19 +6,19 @@ set_property ASYNC_REG TRUE \ [get_cells -hier cdc_sync_stage2_*_reg] set_false_path \ - -from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] \ - -to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] + -from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ + -to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}] # TX FIFO set_max_delay \ -from $ctrl_clk \ - -to [get_cells -hier out_data_reg* -filter {PRIMITIVE_SUBGROUP == flop && NAME =~ *tx_sync*}] \ + -to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *tx_sync*}] \ [get_property PERIOD $data_clk] -datapath_only # RX FIFO set_max_delay \ -from $data_clk \ - -to [get_cells -hier out_data_reg* -filter {PRIMITIVE_SUBGROUP == flop && NAME =~ *rx_sync*}] \ + -to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *rx_sync*}] \ [get_property PERIOD $ctrl_clk] -datapath_only # Reset