axi_i2s_adi: Make constraints work on UltraScale
The 'PRIMITIVE_SUBGROUP == flop' filter only works on 7-Series. Replace it with 'IS_SEQUENTIAL' which works on both 7-Series and UltraScale. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
3ab3d3d111
commit
38f495b2cf
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@ -6,19 +6,19 @@ set_property ASYNC_REG TRUE \
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[get_cells -hier cdc_sync_stage2_*_reg]
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[get_cells -hier cdc_sync_stage2_*_reg]
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set_false_path \
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set_false_path \
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-from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] \
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-from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \
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-to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop}]
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-to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}]
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# TX FIFO
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# TX FIFO
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set_max_delay \
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set_max_delay \
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-from $ctrl_clk \
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-from $ctrl_clk \
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-to [get_cells -hier out_data_reg* -filter {PRIMITIVE_SUBGROUP == flop && NAME =~ *tx_sync*}] \
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-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *tx_sync*}] \
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[get_property PERIOD $data_clk] -datapath_only
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[get_property PERIOD $data_clk] -datapath_only
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# RX FIFO
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# RX FIFO
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set_max_delay \
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set_max_delay \
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-from $data_clk \
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-from $data_clk \
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-to [get_cells -hier out_data_reg* -filter {PRIMITIVE_SUBGROUP == flop && NAME =~ *rx_sync*}] \
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-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *rx_sync*}] \
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[get_property PERIOD $ctrl_clk] -datapath_only
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[get_property PERIOD $ctrl_clk] -datapath_only
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# Reset
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# Reset
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