From 3918d43cd12c42bf379b511f9cfaeb79dcbc7fcd Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Fri, 11 Sep 2020 13:14:33 +0100
Subject: [PATCH] adrv9001/zcu102: Add TDD sync to PMOD0 J55.1

---
 projects/adrv9001/zcu102/system_constr.xdc |  2 ++
 projects/adrv9001/zcu102/system_top.v      | 20 ++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/projects/adrv9001/zcu102/system_constr.xdc b/projects/adrv9001/zcu102/system_constr.xdc
index 14dfdcb4d..af18449fd 100644
--- a/projects/adrv9001/zcu102/system_constr.xdc
+++ b/projects/adrv9001/zcu102/system_constr.xdc
@@ -42,3 +42,5 @@ set_property  -dict {PACKAGE_PIN V7    IOSTANDARD LVCMOS18}  [get_ports platform
 set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_p]
 set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p]
 
+set_property  -dict {PACKAGE_PIN A20   IOSTANDARD LVCMOS33} [get_ports tdd_sync]   ;#PMOD0_0 J55.1
+
diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v
index ae6a6a177..94716a2c7 100644
--- a/projects/adrv9001/zcu102/system_top.v
+++ b/projects/adrv9001/zcu102/system_top.v
@@ -122,7 +122,9 @@ module system_top (
 
   inout                   sm_fan_tach,
   input                   vadj_err,
-  output                  platform_status
+  output                  platform_status,
+
+  inout                   tdd_sync
 );
   // internal registers
   reg         [  2:0] mcs_sync_m = 'd0;
@@ -140,6 +142,9 @@ module system_top (
 
   wire fpga_ref_clk;
   wire fpga_mcs_in;
+  wire tdd_sync_loc;
+  wire tdd_sync_i;
+  wire tdd_sync_cntr;
 
   // instantiations
 
@@ -175,7 +180,7 @@ module system_top (
     .dio_t ({gpio_t[47:32]}),
     .dio_i ({gpio_o[47:32]}),
     .dio_o ({gpio_i[47:32]}),
-    .dio_p ({sm_fan_tach,  // 47 
+    .dio_p ({sm_fan_tach,  // 47
              reset_trx,    // 46
              mode,         // 45
              gp_int,       // 44
@@ -208,6 +213,14 @@ module system_top (
 
   assign spi_en = spi_csn[0];
 
+  assign tdd_sync_loc = gpio_o[56];
+
+  // tdd_sync_loc - local sync signal from a GPIO or other source
+  // tdd_sync - external sync 
+
+  assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
+  assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
+
   system_wrapper i_system_wrapper (
     .ref_clk (fpga_ref_clk),
     .mssi_sync (mssi_sync),
@@ -264,6 +277,9 @@ module system_top (
     .gpio_tx1_enable_in (gpio_tx1_enable_in),
     .gpio_tx2_enable_in (gpio_tx2_enable_in),
 
+    .tdd_sync (tdd_sync_i),
+    .tdd_sync_cntr (tdd_sync_cntr),
+
     .gpio_i (gpio_i),
     .gpio_o (gpio_o),
     .gpio_t (gpio_t),