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adrv9001/zcu102: Add TDD sync to PMOD0 J55.1

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Laszlo Nagy 2020-09-11 13:14:33 +01:00 committed by Laszlo Nagy
parent fe9f72db9c
commit 3918d43cd1
2 changed files with 20 additions and 2 deletions
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2
projects/adrv9001/zcu102/system_constr.xdc
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@ -42,3 +42,5 @@ set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports platform
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_p]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p]
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports tdd_sync] ;#PMOD0_0 J55.1

18
projects/adrv9001/zcu102/system_top.v
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@ -122,7 +122,9 @@ module system_top (
inout sm_fan_tach,
input vadj_err,
output platform_status
output platform_status,
inout tdd_sync
);
// internal registers
reg [ 2:0] mcs_sync_m = 'd0;
@ -140,6 +142,9 @@ module system_top (
wire fpga_ref_clk;
wire fpga_mcs_in;
wire tdd_sync_loc;
wire tdd_sync_i;
wire tdd_sync_cntr;
// instantiations
@ -208,6 +213,14 @@ module system_top (
assign spi_en = spi_csn[0];
assign tdd_sync_loc = gpio_o[56];
// tdd_sync_loc - local sync signal from a GPIO or other source
// tdd_sync - external sync
assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
system_wrapper i_system_wrapper (
.ref_clk (fpga_ref_clk),
.mssi_sync (mssi_sync),
@ -264,6 +277,9 @@ module system_top (
.gpio_tx1_enable_in (gpio_tx1_enable_in),
.gpio_tx2_enable_in (gpio_tx2_enable_in),
.tdd_sync (tdd_sync_i),
.tdd_sync_cntr (tdd_sync_cntr),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),