diff --git a/docs/projects/ad4630_fmc/adaq42xx_hdl_cm0_cz2_1.svg b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm0_cz2_1.svg
new file mode 100644
index 000000000..d4966f64b
--- /dev/null
+++ b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm0_cz2_1.svg
@@ -0,0 +1,2500 @@
+
+
diff --git a/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg
new file mode 100644
index 000000000..c7a14e353
--- /dev/null
+++ b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg
@@ -0,0 +1,2664 @@
+
+
diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst
index 1607a7a4d..3384be07d 100644
--- a/docs/projects/ad4630_fmc/index.rst
+++ b/docs/projects/ad4630_fmc/index.rst
@@ -37,6 +37,13 @@ integrates all critical power supply and reference bypass capacitors, reducing
the footprint and system component count, and lessening sensitivity to board
layout.
+The ADAQ4224 is a μModule® precision data acquisition (DAQ) signal chain
+solution that reduces the development cycle of a precision measurement system
+by transferring the signal chain design challenge of component selection,
+optimization, and layout from the designer to the device. With a guaranteed
+maximum ±TBD ppm INL and no missing codes at 24 bits, the ADAQ4224 achieves
+unparalleled precision from −40°C to +85°C.
+
The HDL reference design for the :adi:`EVAL-AD4630_FMCZ` and
:adi:`EVAL-AD4030_FMCZ` provides all the interfaces that are necessary to
interact with the device using a Xilinx FPGA development board. The design has
@@ -61,6 +68,8 @@ Supported boards
- :adi:`EVAL-AD4030-24FMCZ `
- :adi:`EVAL-AD4630-16FMCZ `
- :adi:`EVAL-AD4630-24FMCZ `
+- EVAL-ADAQ4224-FMCZ
+- EVAL-ISO-4224-FMCZ
Supported devices
-------------------------------------------------------------------------------
@@ -68,6 +77,7 @@ Supported devices
- :adi:`AD4030-24`
- :adi:`AD4630-16`
- :adi:`AD4630-24`
+- ADAQ4224
Supported carriers
-------------------------------------------------------------------------------
@@ -121,6 +131,11 @@ where the two signals will have different frequencies.
:align: center
:alt: AD4630_FMC SPI mode - transfer zone 2 block diagram
+.. image:: adaq42xx_hdl_cm0_cz2_1.svg
+ :width: 800
+ :align: center
+ :alt: ADAQ4224_FMC SPI mode - transfer zone 2 block diagram
+
Echo clock mode - transfer zone 2
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -135,6 +150,11 @@ mode.
:align: center
:alt: AD4630_FMC Echo clock mode - transfer zone 2 block diagram
+.. image:: adaq42xx_hdl_cm1_cz2_1.svg
+ :width: 800
+ :align: center
+ :alt: ADAQ4224_FMC Echo clock mode - transfer zone 2 block diagram
+
The design supports the following interface and clock modes both in SDR and DDR:
================== ================== ================== ==================
@@ -176,8 +196,14 @@ spi_ad463x_axi_regmap 0x44A0_0000
axi_ad463x_dma 0x44A3_0000
spi_clkgen 0x44A7_0000
cnv_generator 0x44B0_0000
+sync_generator* 0x44C0_0000
======================== ===========
+.. admonition:: Legend
+ :class: note
+
+ - ``*`` instantiated, but only used for ADAQ4224 with isolated power supply
+
I2C connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -195,11 +221,21 @@ I2C connections
- axi_iic_fmc
- 0x4162_0000
- ---
- * - PL
- - iic_main
- - axi_iic_main
- - 0x4160_0000
- - ---
+ * -
+ -
+ -
+ - 0x50
+ - eeprom
+ * -
+ -
+ -
+ - 0x5F
+ - temperature sensor *
+
+.. admonition:: Legend
+ :class: note
+
+ - ``*`` Temperature Sensor HW Monitor is present only in ADAQ4224
SPI connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -240,7 +276,25 @@ The Software GPIO number is calculated as follows:
- INOUT
- 32
- 86
-
+ * - adaq42xx_pgia_mux[0]*
+ - INOUT
+ - 33
+ - 87
+ * - adaq42xx_pgia_mux[1]*
+ - INOUT
+ - 34
+ - 88
+ * - max17687_rst**
+ - INOUT
+ - 35
+ - 89
+
+.. admonition:: Legend
+ :class: note
+
+ - ``*`` instantiated, but used for ADAQ4224 only
+ - ``**`` instantiated, but used for ADAQ4224 with isolated power supply
+
Interrupts
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/projects/index.rst b/docs/projects/index.rst
index 9a388cf7f..bbc8c1c22 100644
--- a/docs/projects/index.rst
+++ b/docs/projects/index.rst
@@ -19,7 +19,7 @@ Contents
:maxdepth: 1
AD4134-FMC
- AD4630-FMC
+ AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
AD469X-FMC
AD5766-SDZ
AD7134-FMC
diff --git a/projects/ad4630_fmc/common/ad4030_fmc.txt b/projects/ad4630_fmc/common/ad4030_fmc.txt
new file mode 100644
index 000000000..daf367de5
--- /dev/null
+++ b/projects/ad4630_fmc/common/ad4030_fmc.txt
@@ -0,0 +1,20 @@
+# ad4030
+
+FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
+
+G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
+G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
+G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
+G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
+H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
+H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
+H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
+H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
+H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
+D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
+D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
+D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
+D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
+D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
+C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
+C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A
diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl
index 39a0dbd04..96f37f96d 100644
--- a/projects/ad4630_fmc/common/ad463x_bd.tcl
+++ b/projects/ad4630_fmc/common/ad463x_bd.tcl
@@ -21,6 +21,9 @@ set cnv_ref_clk 100
# NOTE: this is a default value, software may or may not change this
set adc_sampling_rate 1000000
+# specify the MAX17687 and LT8608 SYNC signal frequency (400KHz)
+set max17687_sync_freq 400000
+
#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad463x_spi
create_bd_port -dir O ad463x_spi_sclk
@@ -34,6 +37,8 @@ create_bd_port -dir I ad463x_busy
create_bd_port -dir O ad463x_cnv
create_bd_port -dir I ad463x_ext_clk
+create_bd_port -dir O max17687_sync_clk
+
## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
ad_ip_instance axi_clkgen spi_clkgen
@@ -70,6 +75,9 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3
## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
+## setup the pulse period for the MAX17687 and LT8608 SYNC signal
+set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))]
+
ad_ip_instance axi_pwm_gen cnv_generator
ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
@@ -78,6 +86,11 @@ ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1
+ad_ip_instance axi_pwm_gen sync_generator
+ad_ip_parameter sync_generator CONFIG.N_PWMS 1
+ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
+ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]
+
ad_ip_instance spi_axis_reorder data_reorder
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
@@ -171,15 +184,18 @@ if {$CAPTURE_ZONE == 1} {
}
ad_connect ad463x_cnv cnv_generator/pwm_1
+ad_connect max17687_sync_clk sync_generator/pwm_0
# clocks
ad_connect $sys_cpu_clk $hier_spi_engine/clk
ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
+ad_connect $sys_cpu_clk sync_generator/s_axi_aclk
ad_connect spi_clk $hier_spi_engine/spi_clk
ad_connect spi_clk data_reorder/axis_aclk
ad_connect spi_clk axi_ad463x_dma/s_axis_aclk
ad_connect ad463x_ext_clk cnv_generator/ext_clk
+ad_connect ad463x_ext_clk sync_generator/ext_clk
# resets
@@ -201,6 +217,7 @@ ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad_cpu_interconnect 0x44b00000 cnv_generator
+ad_cpu_interconnect 0x44c00000 sync_generator
ad_cpu_interconnect 0x44a30000 axi_ad463x_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen
diff --git a/projects/ad4630_fmc/common/adaq42xx_fmc.txt b/projects/ad4630_fmc/common/adaq42xx_fmc.txt
new file mode 100644
index 000000000..5d909d34e
--- /dev/null
+++ b/projects/ad4630_fmc/common/adaq42xx_fmc.txt
@@ -0,0 +1,27 @@
+# adaq42xx
+
+FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
+
+G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
+G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
+G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
+G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
+H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
+H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
+H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
+H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
+H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
+D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
+D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
+D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
+D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
+D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
+C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
+C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A
+
+G12 LA08_P MUX_A0 adaq42xx_pgia_mux[0] LVCMOS25 #N/A
+G13 LA08_N MUX_A1 adaq42xx_pgia_mux[1] LVCMOS25 #N/A
+
+H13 LA07_P RST max17687_rst LVCMOS25 #N/A
+H14 LA07_N EN max17687_en LVCMOS25 #N/A
+D21 LA17_CC_N SYNCFMC max17687_sync_clk LVCMOS25 #N/A
diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md
index ee482e503..29a619872 100644
--- a/projects/ad4630_fmc/zed/README.md
+++ b/projects/ad4630_fmc/zed/README.md
@@ -3,8 +3,9 @@
## Building the design
-The design supports almost all the digital interface modes of AD4630-24, a new
-bit stream should be generated each time when the targeted configuration changes.
+The design supports almost all the digital interface modes of AD463x, AD403x
+and adaq42xx a new bit stream should be generated each time when the targeted
+configuration changes.
Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
data capture and capture zone 2.
@@ -18,7 +19,16 @@ data capture and capture zone 2.
| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
-**Example:** make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
+**Example:**
+ make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
+ make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
+ make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
+ make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
## Documentation
diff --git a/projects/ad4630_fmc/zed/system_constr.xdc b/projects/ad4630_fmc/zed/system_constr.xdc
index 9f5d3eb4e..1a2dae345 100644
--- a/projects/ad4630_fmc/zed/system_constr.xdc
+++ b/projects/ad4630_fmc/zed/system_constr.xdc
@@ -1,5 +1,5 @@
###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -14,6 +14,13 @@ set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P
+set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
+set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N
+
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC
+
# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]
diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v
index b0dd329cf..cf55b9eea 100644
--- a/projects/ad4630_fmc/zed/system_top.v
+++ b/projects/ad4630_fmc/zed/system_top.v
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -95,7 +95,13 @@ module system_top #(
input ad463x_ext_clk,
output ad463x_cnv,
input ad463x_busy,
- inout ad463x_resetn
+ inout ad463x_resetn,
+
+ inout [ 1:0] adaq42xx_pgia_mux,
+
+ inout max17687_rst,
+ output max17687_en,
+ output max17687_sync_clk
);
// internal signals
@@ -114,7 +120,8 @@ module system_top #(
// instantiations
- assign gpio_i[63:33] = 31'b0;
+ assign gpio_i[63:36] = 27'b0;
+ assign max17687_en = 1'b1;
ad_data_clk #(
.SINGLE_ENDED (1)
@@ -135,12 +142,14 @@ module system_top #(
.clk (ad463x_echo_sclk_s));
ad_iobuf #(
- .DATA_WIDTH(1)
+ .DATA_WIDTH(4)
) i_ad463x_gpio_iobuf (
- .dio_t(gpio_t[32]),
- .dio_i(gpio_o[32]),
- .dio_o(gpio_i[32]),
- .dio_p(ad463x_resetn));
+ .dio_t(gpio_t[35:32]),
+ .dio_i(gpio_o[35:32]),
+ .dio_o(gpio_i[35:32]),
+ .dio_p ({max17687_rst, // 35
+ adaq42xx_pgia_mux, // 34:33
+ ad463x_resetn})); // 32
ad_iobuf #(
.DATA_WIDTH(32)
@@ -235,6 +244,7 @@ module system_top #(
.ad463x_busy (ad463x_busy),
.ad463x_cnv (ad463x_cnv),
.ad463x_ext_clk (ext_clk_s),
+ .max17687_sync_clk (max17687_sync_clk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));