diff --git a/library/altera/avl_dacfifo/avl_dacfifo_rd.v b/library/altera/avl_dacfifo/avl_dacfifo_rd.v index 70912cab7..80c913d37 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_rd.v +++ b/library/altera/avl_dacfifo/avl_dacfifo_rd.v @@ -54,11 +54,12 @@ module avl_dacfifo_rd #( // Max supported MEM_RATIO is 16 localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH; - localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH : - (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) : - (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) : - (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) : - (DAC_MEM_ADDRESS_WIDTH - 4); + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) : + (MEM_RATIO == 16) ? (DAC_MEM_ADDRESS_WIDTH - 4) : + (DAC_MEM_ADDRESS_WIDTH - 5); localparam AVL_MEM_THRESHOLD_LO = 8; localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - 7; @@ -232,11 +233,12 @@ module avl_dacfifo_rd #( // control the FIFO to prevent overflow, underfloq is monitored // ========================================================================== - assign avl_mem_rd_address_s = (MEM_RATIO == 1) ? avl_mem_rd_address : - (MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] : - (MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] : - (MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] : - avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4]; + assign avl_mem_rd_address_s = (MEM_RATIO == 1) ? avl_mem_rd_address : + (MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] : + (MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] : + (MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] : + (MEM_RATIO == 16) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4] : + avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):5]; assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address_s; @@ -266,11 +268,12 @@ module avl_dacfifo_rd #( // ready, data will be dropped // ========================================================================== - assign dac_mem_wr_address_s = (MEM_RATIO == 1) ? dac_mem_wr_address : - (MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} : - (MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} : - (MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} : - {dac_mem_wr_address, 4'b0}; + assign dac_mem_wr_address_s = (MEM_RATIO == 1) ? dac_mem_wr_address : + (MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} : + (MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} : + (MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} : + (MEM_RATIO == 16) ? {dac_mem_wr_address, 4'b0} : + {dac_mem_wr_address, 5'b0}; assign dac_mem_address_diff_s = {1'b1, dac_mem_wr_address_s} - dac_mem_rd_address; diff --git a/library/altera/avl_dacfifo/avl_dacfifo_wr.v b/library/altera/avl_dacfifo/avl_dacfifo_wr.v index 8a6ed5862..8583d147f 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_wr.v +++ b/library/altera/avl_dacfifo/avl_dacfifo_wr.v @@ -54,15 +54,17 @@ module avl_dacfifo_wr #( output reg avl_xfer_req); localparam MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 - localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : - (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : - (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : - (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : - (DMA_MEM_ADDRESS_WIDTH - 4); - localparam MEM_WIDTH_DIFF = (MEM_RATIO > 8) ? 4 : - (MEM_RATIO > 4) ? 3 : - (MEM_RATIO > 2) ? 2 : - (MEM_RATIO > 1) ? 1 : 1; + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : + (MEM_RATIO == 16) ? (DMA_MEM_ADDRESS_WIDTH - 4) : + (DMA_MEM_ADDRESS_WIDTH - 5); + localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 : + (MEM_RATIO > 8) ? 4 : + (MEM_RATIO > 4) ? 3 : + (MEM_RATIO > 2) ? 2 : + (MEM_RATIO > 1) ? 1 : 1; localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4; localparam DMA_BYTE_DATA_WIDTH = DMA_DATA_WIDTH/8; @@ -176,11 +178,12 @@ module avl_dacfifo_wr #( // write address generation assign dma_mem_address_diff_s = {1'b1, dma_mem_wr_address} - dma_mem_rd_address_s; - assign dma_mem_rd_address_s = (MEM_RATIO == 1) ? dma_mem_rd_address : - (MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} : - (MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} : - (MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} : - {dma_mem_rd_address, 4'b0}; + assign dma_mem_rd_address_s = (MEM_RATIO == 1) ? dma_mem_rd_address : + (MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} : + (MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} : + (MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} : + (MEM_RATIO == 16) ? {dma_mem_rd_address, 4'b0} : + {dma_mem_rd_address, 5'b0}; assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req; always @(posedge dma_clk) begin @@ -362,107 +365,170 @@ module avl_dacfifo_wr #( case (avl_last_beats) 0 : begin case (MEM_RATIO) - 2 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 4 : avl_byteenable <= {48'b0, {16{1'b1}}}; - 8 : avl_byteenable <= {56'b0, {8{1'b1}}}; + 2 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 4 : avl_byteenable <= {48'b0, {16{1'b1}}}; + 8 : avl_byteenable <= {56'b0, {8{1'b1}}}; 16 : avl_byteenable <= {60'b0, {4{1'b1}}}; + 32 : avl_byteenable <= {62'b0, {2{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 1 : begin case (MEM_RATIO) - 4 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 8 : avl_byteenable <= {48'b0, {16{1'b1}}}; + 4 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 8 : avl_byteenable <= {48'b0, {16{1'b1}}}; 16 : avl_byteenable <= {56'b0, {8{1'b1}}}; + 32 : avl_byteenable <= {60'b0, {4{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 2 : begin case (MEM_RATIO) - 4 : avl_byteenable <= {16'b0, {48{1'b1}}}; - 8 : avl_byteenable <= {40'b0, {24{1'b1}}}; + 4 : avl_byteenable <= {16'b0, {48{1'b1}}}; + 8 : avl_byteenable <= {40'b0, {24{1'b1}}}; 16 : avl_byteenable <= {52'b0, {12{1'b1}}}; + 32 : avl_byteenable <= {58'b0, {6{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 3 : begin case (MEM_RATIO) - 8 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 8 : avl_byteenable <= {32'b0, {32{1'b1}}}; 16 : avl_byteenable <= {48'b0, {16{1'b1}}}; + 32 : avl_byteenable <= {56'b0, {8{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 4 : begin case (MEM_RATIO) - 8 : avl_byteenable <= {24'b0, {40{1'b1}}}; + 8 : avl_byteenable <= {24'b0, {40{1'b1}}}; 16 : avl_byteenable <= {44'b0, {20{1'b1}}}; + 32 : avl_byteenable <= {54'b0, {10{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 5 : begin case (MEM_RATIO) - 8 : avl_byteenable <= {16'b0, {48{1'b1}}}; + 8 : avl_byteenable <= {16'b0, {48{1'b1}}}; 16 : avl_byteenable <= {40'b0, {24{1'b1}}}; + 32 : avl_byteenable <= {52'b0, {12{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 6 : begin case (MEM_RATIO) - 8 : avl_byteenable <= {8'b0, {56{1'b1}}}; + 8 : avl_byteenable <= {8'b0, {56{1'b1}}}; 16 : avl_byteenable <= {36'b0, {28{1'b1}}}; + 32 : avl_byteenable <= {50'b0, {14{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 7 : begin case (MEM_RATIO) 16 : avl_byteenable <= {32'b0, {32{1'b1}}}; + 32 : avl_byteenable <= {48'b0, {16{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 8 : begin case (MEM_RATIO) 16 : avl_byteenable <= {28'b0, {36{1'b1}}}; + 32 : avl_byteenable <= {46'b0, {18{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 9 : begin case (MEM_RATIO) 16 : avl_byteenable <= {24'b0, {40{1'b1}}}; + 32 : avl_byteenable <= {44'b0, {20{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 10 : begin case (MEM_RATIO) 16 : avl_byteenable <= {20'b0, {44{1'b1}}}; + 32 : avl_byteenable <= {42'b0, {22{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 11 : begin case (MEM_RATIO) 16 : avl_byteenable <= {16'b0, {48{1'b1}}}; + 32 : avl_byteenable <= {40'b0, {24{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 12 : begin case (MEM_RATIO) 16 : avl_byteenable <= {12'b0, {52{1'b1}}}; + 32 : avl_byteenable <= {38'b0, {26{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 13 : begin case (MEM_RATIO) 16 : avl_byteenable <= {8'b0, {56{1'b1}}}; + 32 : avl_byteenable <= {36'b0, {28{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 14 : begin case (MEM_RATIO) 16 : avl_byteenable <= {4'b0, {60{1'b1}}}; + 32 : avl_byteenable <= {34'b0, {30{1'b1}}}; default : avl_byteenable <= {64{1'b1}}; endcase end 15 : begin - avl_byteenable <= {64{1'b1}}; + case (MEM_RATIO) + 32 : avl_byteenable <= {32'b0, {32{1'b1}}}; + default: avl_byteenable <= {64{1'b1}}; + endcase + end + 16 : begin + avl_byteenable <= {30'b0, {34{1'b1}}}; + end + 17 : begin + avl_byteenable <= {28'b0, {36{1'b1}}}; + end + 18 : begin + avl_byteenable <= {26'b0, {38{1'b1}}}; + end + 19 : begin + avl_byteenable <= {24'b0, {40{1'b1}}}; + end + 20 : begin + avl_byteenable <= {22'b0, {42{1'b1}}}; + end + 21 : begin + avl_byteenable <= {20'b0, {44{1'b1}}}; + end + 22 : begin + avl_byteenable <= {18'b0, {46{1'b1}}}; + end + 23 : begin + avl_byteenable <= {16'b0, {48{1'b1}}}; + end + 24 : begin + avl_byteenable <= {14'b0, {50{1'b1}}}; + end + 25 : begin + avl_byteenable <= {12'b0, {52{1'b1}}}; + end + 26 : begin + avl_byteenable <= {10'b0, {54{1'b1}}}; + end + 27 : begin + avl_byteenable <= {8'b0, {56{1'b1}}}; + end + 28 : begin + avl_byteenable <= {6'b0, {58{1'b1}}}; + end + 29 : begin + avl_byteenable <= {4'b0, {60{1'b1}}}; + end + 30 : begin + avl_byteenable <= {2'b0, {62{1'b1}}}; end default : avl_byteenable <= {64{1'b1}}; endcase