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avl_dacfifo: Add support for MEM_RATIO 32

main
Istvan Csomortani 2017-05-15 14:14:44 +03:00
parent a1539a62b7
commit 398619d866
2 changed files with 110 additions and 41 deletions
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9
library/altera/avl_dacfifo/avl_dacfifo_rd.v
View File

@ -58,7 +58,8 @@ module avl_dacfifo_rd #(
(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) : (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) :
(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) : (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) :
(MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) : (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) :
(DAC_MEM_ADDRESS_WIDTH - 4); (MEM_RATIO == 16) ? (DAC_MEM_ADDRESS_WIDTH - 4) :
(DAC_MEM_ADDRESS_WIDTH - 5);
localparam AVL_MEM_THRESHOLD_LO = 8; localparam AVL_MEM_THRESHOLD_LO = 8;
localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - 7; localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - 7;
@ -236,7 +237,8 @@ module avl_dacfifo_rd #(
(MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] : (MEM_RATIO == 2) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):1] :
(MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] : (MEM_RATIO == 4) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):2] :
(MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] : (MEM_RATIO == 8) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):3] :
avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4]; (MEM_RATIO == 16) ? avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):4] :
avl_mem_rd_address[(DAC_MEM_ADDRESS_WIDTH-1):5];
assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address_s; assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address_s;
@ -270,7 +272,8 @@ module avl_dacfifo_rd #(
(MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} : (MEM_RATIO == 2) ? {dac_mem_wr_address, 1'b0} :
(MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} : (MEM_RATIO == 4) ? {dac_mem_wr_address, 2'b0} :
(MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} : (MEM_RATIO == 8) ? {dac_mem_wr_address, 3'b0} :
{dac_mem_wr_address, 4'b0}; (MEM_RATIO == 16) ? {dac_mem_wr_address, 4'b0} :
{dac_mem_wr_address, 5'b0};
assign dac_mem_address_diff_s = {1'b1, dac_mem_wr_address_s} - dac_mem_rd_address; assign dac_mem_address_diff_s = {1'b1, dac_mem_wr_address_s} - dac_mem_rd_address;

74
library/altera/avl_dacfifo/avl_dacfifo_wr.v
View File

@ -58,8 +58,10 @@ module avl_dacfifo_wr #(
(MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
(MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
(MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
(DMA_MEM_ADDRESS_WIDTH - 4); (MEM_RATIO == 16) ? (DMA_MEM_ADDRESS_WIDTH - 4) :
localparam MEM_WIDTH_DIFF = (MEM_RATIO > 8) ? 4 : (DMA_MEM_ADDRESS_WIDTH - 5);
localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 :
(MEM_RATIO > 8) ? 4 :
(MEM_RATIO > 4) ? 3 : (MEM_RATIO > 4) ? 3 :
(MEM_RATIO > 2) ? 2 : (MEM_RATIO > 2) ? 2 :
(MEM_RATIO > 1) ? 1 : 1; (MEM_RATIO > 1) ? 1 : 1;
@ -180,7 +182,8 @@ module avl_dacfifo_wr #(
(MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} : (MEM_RATIO == 2) ? {dma_mem_rd_address, 1'b0} :
(MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} : (MEM_RATIO == 4) ? {dma_mem_rd_address, 2'b0} :
(MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} : (MEM_RATIO == 8) ? {dma_mem_rd_address, 3'b0} :
{dma_mem_rd_address, 4'b0}; (MEM_RATIO == 16) ? {dma_mem_rd_address, 4'b0} :
{dma_mem_rd_address, 5'b0};
assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req; assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req;
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
@ -366,6 +369,7 @@ module avl_dacfifo_wr #(
4 : avl_byteenable <= {48'b0, {16{1'b1}}}; 4 : avl_byteenable <= {48'b0, {16{1'b1}}};
8 : avl_byteenable <= {56'b0, {8{1'b1}}}; 8 : avl_byteenable <= {56'b0, {8{1'b1}}};
16 : avl_byteenable <= {60'b0, {4{1'b1}}}; 16 : avl_byteenable <= {60'b0, {4{1'b1}}};
32 : avl_byteenable <= {62'b0, {2{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -374,6 +378,7 @@ module avl_dacfifo_wr #(
4 : avl_byteenable <= {32'b0, {32{1'b1}}}; 4 : avl_byteenable <= {32'b0, {32{1'b1}}};
8 : avl_byteenable <= {48'b0, {16{1'b1}}}; 8 : avl_byteenable <= {48'b0, {16{1'b1}}};
16 : avl_byteenable <= {56'b0, {8{1'b1}}}; 16 : avl_byteenable <= {56'b0, {8{1'b1}}};
32 : avl_byteenable <= {60'b0, {4{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -382,6 +387,7 @@ module avl_dacfifo_wr #(
4 : avl_byteenable <= {16'b0, {48{1'b1}}}; 4 : avl_byteenable <= {16'b0, {48{1'b1}}};
8 : avl_byteenable <= {40'b0, {24{1'b1}}}; 8 : avl_byteenable <= {40'b0, {24{1'b1}}};
16 : avl_byteenable <= {52'b0, {12{1'b1}}}; 16 : avl_byteenable <= {52'b0, {12{1'b1}}};
32 : avl_byteenable <= {58'b0, {6{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -389,6 +395,7 @@ module avl_dacfifo_wr #(
case (MEM_RATIO) case (MEM_RATIO)
8 : avl_byteenable <= {32'b0, {32{1'b1}}}; 8 : avl_byteenable <= {32'b0, {32{1'b1}}};
16 : avl_byteenable <= {48'b0, {16{1'b1}}}; 16 : avl_byteenable <= {48'b0, {16{1'b1}}};
32 : avl_byteenable <= {56'b0, {8{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -396,6 +403,7 @@ module avl_dacfifo_wr #(
case (MEM_RATIO) case (MEM_RATIO)
8 : avl_byteenable <= {24'b0, {40{1'b1}}}; 8 : avl_byteenable <= {24'b0, {40{1'b1}}};
16 : avl_byteenable <= {44'b0, {20{1'b1}}}; 16 : avl_byteenable <= {44'b0, {20{1'b1}}};
32 : avl_byteenable <= {54'b0, {10{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -403,6 +411,7 @@ module avl_dacfifo_wr #(
case (MEM_RATIO) case (MEM_RATIO)
8 : avl_byteenable <= {16'b0, {48{1'b1}}}; 8 : avl_byteenable <= {16'b0, {48{1'b1}}};
16 : avl_byteenable <= {40'b0, {24{1'b1}}}; 16 : avl_byteenable <= {40'b0, {24{1'b1}}};
32 : avl_byteenable <= {52'b0, {12{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
@ -410,59 +419,116 @@ module avl_dacfifo_wr #(
case (MEM_RATIO) case (MEM_RATIO)
8 : avl_byteenable <= {8'b0, {56{1'b1}}}; 8 : avl_byteenable <= {8'b0, {56{1'b1}}};
16 : avl_byteenable <= {36'b0, {28{1'b1}}}; 16 : avl_byteenable <= {36'b0, {28{1'b1}}};
32 : avl_byteenable <= {50'b0, {14{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
7 : begin 7 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {32'b0, {32{1'b1}}}; 16 : avl_byteenable <= {32'b0, {32{1'b1}}};
32 : avl_byteenable <= {48'b0, {16{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
8 : begin 8 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {28'b0, {36{1'b1}}}; 16 : avl_byteenable <= {28'b0, {36{1'b1}}};
32 : avl_byteenable <= {46'b0, {18{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
9 : begin 9 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {24'b0, {40{1'b1}}}; 16 : avl_byteenable <= {24'b0, {40{1'b1}}};
32 : avl_byteenable <= {44'b0, {20{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
10 : begin 10 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {20'b0, {44{1'b1}}}; 16 : avl_byteenable <= {20'b0, {44{1'b1}}};
32 : avl_byteenable <= {42'b0, {22{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
11 : begin 11 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {16'b0, {48{1'b1}}}; 16 : avl_byteenable <= {16'b0, {48{1'b1}}};
32 : avl_byteenable <= {40'b0, {24{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
12 : begin 12 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {12'b0, {52{1'b1}}}; 16 : avl_byteenable <= {12'b0, {52{1'b1}}};
32 : avl_byteenable <= {38'b0, {26{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
13 : begin 13 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {8'b0, {56{1'b1}}}; 16 : avl_byteenable <= {8'b0, {56{1'b1}}};
32 : avl_byteenable <= {36'b0, {28{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
14 : begin 14 : begin
case (MEM_RATIO) case (MEM_RATIO)
16 : avl_byteenable <= {4'b0, {60{1'b1}}}; 16 : avl_byteenable <= {4'b0, {60{1'b1}}};
32 : avl_byteenable <= {34'b0, {30{1'b1}}};
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase
end end
15 : begin 15 : begin
avl_byteenable <= {64{1'b1}}; case (MEM_RATIO)
32 : avl_byteenable <= {32'b0, {32{1'b1}}};
default: avl_byteenable <= {64{1'b1}};
endcase
end
16 : begin
avl_byteenable <= {30'b0, {34{1'b1}}};
end
17 : begin
avl_byteenable <= {28'b0, {36{1'b1}}};
end
18 : begin
avl_byteenable <= {26'b0, {38{1'b1}}};
end
19 : begin
avl_byteenable <= {24'b0, {40{1'b1}}};
end
20 : begin
avl_byteenable <= {22'b0, {42{1'b1}}};
end
21 : begin
avl_byteenable <= {20'b0, {44{1'b1}}};
end
22 : begin
avl_byteenable <= {18'b0, {46{1'b1}}};
end
23 : begin
avl_byteenable <= {16'b0, {48{1'b1}}};
end
24 : begin
avl_byteenable <= {14'b0, {50{1'b1}}};
end
25 : begin
avl_byteenable <= {12'b0, {52{1'b1}}};
end
26 : begin
avl_byteenable <= {10'b0, {54{1'b1}}};
end
27 : begin
avl_byteenable <= {8'b0, {56{1'b1}}};
end
28 : begin
avl_byteenable <= {6'b0, {58{1'b1}}};
end
29 : begin
avl_byteenable <= {4'b0, {60{1'b1}}};
end
30 : begin
avl_byteenable <= {2'b0, {62{1'b1}}};
end end
default : avl_byteenable <= {64{1'b1}}; default : avl_byteenable <= {64{1'b1}};
endcase endcase