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AD9361: Altera, modified address width so that all registers are accessible 

Modified qsys project with the new address span
main
Adrian Costina 2014-07-08 10:41:51 +03:00
parent 10c21a343a
commit 39ac29bb01
3 changed files with 7 additions and 7 deletions
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6
library/axi_ad9361/axi_ad9361_alt.v
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@ -223,7 +223,7 @@ module axi_ad9361_alt (
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 13:0] s_axi_awaddr;
input [ 15:0] s_axi_awaddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
@ -242,7 +242,7 @@ module axi_ad9361_alt (
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [ 13:0] s_axi_araddr;
input [ 15:0] s_axi_araddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
@ -327,7 +327,7 @@ module axi_ad9361_alt (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awaddr ({16'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),

4
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -81,7 +81,7 @@ add_interface s_axi axi4 end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 14
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
@ -91,7 +91,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 14
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2

4
projects/fmcomms2/c5soc/system_bd.qsys
View File

@ -106,7 +106,7 @@
{
datum baseAddress
{
value = "32768";
value = "131072";
type = "String";
}
}
@ -915,7 +915,7 @@
start="sys_hps.h2f_lw_axi_master"
end="axi_ad9361.s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection