From 39e073e6bf58cb952d87a2c2cde5cf561d608b4f Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 10 Feb 2022 13:13:57 +0000 Subject: [PATCH] adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens In some cases (GTX2) the transceiver may gate the out_clk when it is in reset. This will stop the clock generators from getting a clock prior removing the reset of the XCVR. The XCVR has a requirement of running user clock while removing the reset. The correct sequence must be : Enable device clocks (user clock) Remove the reset from the XCVR --- projects/adrv9371x/common/adrv9371x_bd.tcl | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl index d27c7ee81..e10371d41 100644 --- a/projects/adrv9371x/common/adrv9371x_bd.tcl +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -45,6 +45,8 @@ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl # ad9371 +create_bd_port -dir I ref_clk + create_bd_port -dir I dac_fifo_bypass create_bd_port -dir I adc_fir_filter_active create_bd_port -dir I dac_fir_filter_active @@ -220,14 +222,14 @@ ad_connect $sys_cpu_clk util_ad9371_xcvr/up_clk # Tx ad_connect ad9371_tx_device_clk axi_ad9371_tx_clkgen/clk_0 ad_xcvrcon util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd {1 2 3 0} ad9371_tx_device_clk {} $MAX_TX_NUM_OF_LANES -ad_connect util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk +ad_connect ref_clk axi_ad9371_tx_clkgen/clk ad_xcvrpll $tx_ref_clk util_ad9371_xcvr/qpll_ref_clk_0 ad_xcvrpll axi_ad9371_tx_xcvr/up_pll_rst util_ad9371_xcvr/up_qpll_rst_0 # Rx ad_connect ad9371_rx_device_clk axi_ad9371_rx_clkgen/clk_0 ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd {} ad9371_rx_device_clk {} $MAX_RX_NUM_OF_LANES -ad_connect util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk +ad_connect ref_clk axi_ad9371_rx_clkgen/clk for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} { set ch [expr $i] ad_xcvrpll $rx_ref_clk util_ad9371_xcvr/cpll_ref_clk_$ch @@ -237,7 +239,7 @@ for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} { # Rx - OBS ad_connect ad9371_rx_os_device_clk axi_ad9371_rx_os_clkgen/clk_0 ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd {} ad9371_rx_os_device_clk {} $MAX_RX_OS_NUM_OF_LANES -ad_connect util_ad9371_xcvr/rx_out_clk_$MAX_RX_NUM_OF_LANES axi_ad9371_rx_os_clkgen/clk +ad_connect ref_clk axi_ad9371_rx_os_clkgen/clk for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} { # channel indexing starts from the last RX set ch [expr $MAX_RX_NUM_OF_LANES + $i]